UPSD3354DV-40U6 Datasheet, PDF (68/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

MCU clock generation
14 MCU clock generation
UPSD33xx
Internal system clocks generated by the clock generation unit are derived from the signal,
XTAL1, shown in Figure 13 on page 69. XTAL1 has a frequency f_OSC, which comes directly
from the external crystal or oscillator device. The SFR named CCON0 (Table 27 on
page 69) controls the clock generation unit.
There are two clock signals produced by the clock generation unit:
● MCU_CLK
● PERIPH_CLK
14.1 MCU_CLK
This clock drives the 8032 MCU core and the watchdog timer (WDT). The frequency of
MCU_CLK is equal to f_OSC by default, but it can be divided by as much as 2048, shown in
Figure 13 on page 69. The bits CPUPS[2:0] select one of eight different divisors, ranging
) ^{from 2 to 2048. The new frequency is available immediately after the CPUPS[2:0] bits are}
t(s ^{written. The final frequency of MCU_CLK is fMCU.}
c MCU_CLK is blocked by either bit, PD or IDL, in the SFR named PCON during MCU Power-
u _{down mode or Idle mode respectively.}
rod ^{MCU_CLK clock can be further divided as required for use in the WDT. See details of the}
WDT in Section 19: Supervisory functions on page 89.
lete ^P _14.2
Obsolete ^{Product(s) - Obso 14.2.1}
PERIPH_CLK
This clock drives all the UPSD33xx peripherals except the WDT. The Frequency of
PERIPH_CLK is always f_OSC. Each of the peripherals can independently divide
PERIPH_CLK to scale it appropriately for use.
PERIPH_CLK runs at all times except when blocked by the PD bit in the SFR named PCON
during MCU Power-down mode.
JTAG interface clock
The JTAG interface for ISP and for debugging uses the externally supplied JTAG clock,
coming in on pin TCK. This means the JTAG ISP interface is always available, and the JTAG
debug interface is available when enabled, even during MCU Idle mode and Power-down
mode.
However, since the MCU participates in the JTAG debug process, and MCU_CLK is halted
during Idle and Power-down modes, the majority of debug functions are not available during
these low power modes. But the JTAG debug interface is capable of executing a reset
command while in these low power modes, which will exit back to normal operating mode
where all debug commands are available again.
The CCON0 SFR contains a bit, DBGCE, which enables the breakpoint comparators inside
the JTAG debug Unit when set. DBGCE is set by default after reset, and firmware may clear
this bit at run-time. Disabling these comparators will reduce current consumption on the
MCU module, and it’s recommended to do so if the debug unit will not be used (such as in
the production version of an end-product).
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Doc ID 9685 Rev 7