UPSD3354DV-40U6 Datasheet, PDF (121/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
IrDA interface
Table 69.
Bit
5
4-0
RDACON register bit definition (continued)
Symbol
R/W
Definition
PULSE
IrDA Pulse Modulation Select
RW
0 = 1.627µs
1 = 3/16 bit time pulses
CDIV[4:0]
RW
Specify Clock Divider (see Figure 70 on page 121)
22.1 Pulse width selection
The IrDA interface has two ways to modulate the standard UART1 serial stream:
1. An IrDA data pulse will have a constant pulse width for any bit time, regardless of the
selected baud rate.
2. An IrDA data pulse will have a pulse width that is proportional to the bit time of the
selected baud rate. In this case, an IrDA data pulse width is 3/16 of its bit time, as
) _{shown in Figure 36 on page 120.}
t(s _{The PULSE bit in the SFR named IRDACON determines which method above will be used.}
uc _{According to the IrDA physical layer specification, for all baud rates at 115.2k bps and below,}
d _{the minimum data pulse width is 1.41µs. For a baud rate of 115.2k bps, the maximum pulse}
ro _{width 2.23µs. If a constant pulse width is to be used for all baud rates (PULSE bit = 0), the}
P _{ideal general pulse width is 1.63µs, derived from the bit time of the fastest baud rate (8.68µs}
te ^{bit time for 115.2k bps rate), multiplied by the proportion, 3/16.}
le To produce this fixed data pulse width when the PULSE bit = 0, a prescaler is needed to
o _{generate an internal reference clock, SIRClk, shown in Figure 35 on page 119. SIRClk is}
bs ^{derived by dividing the oscillator clock frequency, fOSC, using the five bits CDIV[4:0] in the}
SFR named IRDACON. A divisor must be chosen to produce a frequency for SIRClk that
O _{lies between 1.34 MHz and 2.13 MHz, but it is best to choose a divisor value that produces}
) ^{- SIRClk frequency as close to 1.83 MHz as possible, because SIRClk at 1.83 MHz will}
t(s ^{produce an fixed IrDA data pulse width of 1.63µs. Table 70 provides recommended values}
for CDIV[4:0] based on several different values of f_OSC.
uc _{For reference, SIRClk of 2.13 MHz will generate a fixed IrDA data pulse width of 1.41µs, and}
d _{SIRClk of 1.34 MHz will generate a fixed data pulse width of 2.23µs.}
Pro _{Table 70. Recommended CDIV[4:0] values to generate SIRClk}
te ^{(default CDIV[4:0] = 0Fh, 15 decimal)}
le ^fOSC ^(MHz)
Value in CDIV[4:0]
Resulting f_SIRCLK (MHz)
so ^40.00
16h, 22 decimal
1.82
Ob ^{36.864, or 36.00}
14h, 20 decimal
1.84, or 1.80
24.00
0Dh, 13 decimal
1.84
11.059, or 12.00
7.3728⁽¹⁾
06h, 6 decimal
04h, 4 decimal
1.84, or 2.00
1.84
1. When PULSE bit = 0 (fixed data pulse width), this is minimum recommended f_OSC because CDIV[4:0]
must be 4 or greater.
Doc ID 9685 Rev 7
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