UPSD3354DV-40U6 Datasheet, PDF (112/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Serial UART interfaces
UPSD33xx
Table 67. Commonly used baud rates generated from Timer 1 (continued)
Timer 1
UART
mode
f_OSC (MHz)
Desired
baud rate
Resultant
baud rate
Baud rate
deviation
SMOD bit
in PCON
C/T Bit in
TMOD
Timer
mode in
TMOD
Modes 1 or
3
3.6864
9600 Hz 9600 Hz
0
1
0
2
Modes 1 or
3
1.8432
9600 Hz 9600 Hz
0
1
0
2
Modes 1 or
3
1.8432
4800 Hz 4800 Hz
0
1
0
2
TH1
Reload
value
(hex)
FE
FF
FE
21.4 More about UART mode 0
Refer to the block diagram in Figure 27 on page 113, and timing diagram in Figure 28 on
t(s) ^{page 113.}
c ^{Transmission is initiated by any instruction which writes to the SFR named SBUF. At the end}
u _{of a write operation to SBUF, a 1 is loaded into the 9th position of the transmit shift register}
d _{and tells the TX Control unit to begin a transmission. Transmission begins on the following}
ro MCU machine cycle, when the “SEND” signal is active in Figure 28 on page 113.
P _{SEND enables the output of the shift register to the alternate function on the port containing}
te pin RxD, and also enables the SHIFT CLOCK signal to the alternate function on the port
le ^{containing the pin, TxD. At the end of each SHIFT CLOCK in which SEND is active, the}
o contents of the transmit shift register are shifted to the right one position.
bs As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte
O ^{is at the output position of the shift register, then the '1' that was initially loaded into the 9th}
- position, is just to the left of the MSB, and all positions to the left of that contain zeros. This
) _{condition flags the TX Control unit to do one last shift, then deactivate SEND, and then set}
t(s ^{the interrupt flag TI. Both of these actions occur at S1P1.}
c _{Reception is initiated by the condition REN = 1 and RI = 0. At the end of the next MCU}
u _{machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and}
rod ^{in the next clock phase activates RECEIVE. RECEIVE enables the SHIFT CLOCK signal to}
the alternate function on the port containing the pin, TxD. Each pulse of SHIFT CLOCK
P _{moves the contents of the receive shift register one position to the left while RECEIVE is}
te^{active. The value that comes in from the right is the value that was sampled at the RxD pin.}
le^{As data bits come in from the right, 1s shift out to the left. When the 0 that was initially}
o loaded into the right-most position arrives at the left-most position in the shift register, it flags
s _{the RX Control unit to do one last shift, and then it loads SBUF. After this, RECEIVE is}
Ob ^{cleared, and the receive interrupt flag RI is set.}
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Doc ID 9685 Rev 7