UPSD3354DV-40U6 Datasheet, PDF (170/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
27.1.15 JTAG port
In-system programming (ISP) can be performed through the JTAG signals on Port C. This
serial interface allows programming of the entire PSD module device or subsections of the
PSD module (for example, only Flash memory but not the PLDs) without the participation of
the 8032. A blank UPSD33xx device soldered to a circuit board can be completely
programmed in 10 to 25 seconds. The four basic JTAG signals on Port C; TMS, TCK, TDI,
and TDO form the IEEE-1149.1 interface. The PSD module does not implement the IEEE-
1149.1 Boundary Scan functions, but uses the JTAG interface for ISP an 8032 debug. The
PSD module can reside in a standard JTAG chain with other JTAG devices and it will remain
in BYPASS mode when other devices perform JTAG functions. ISP programming time can
be reduced as much as 30% by using two optional JTAG signals on Port C, TSTAT and
TERR, in addition to TMS, TCK, TDI and TDO, and this is referred to as “6-pin JTAG”. The
FlashLINK JTAG programming cable is available from STMicroelectronics and PSDsoft
Express software is available at no charge from www.st.com/mcu. More JTAG ISP
information maybe found in the section titled “JTAG ISP and debug” on page 137.
The MCU module is also included in the JTAG chain within the UPSD33xx device for 8032
debugging and emulation. While debugging, the PSD module is in BYPASS mode.
) ^{Conversely, during ISP, the MCU module is in BYPASS mode.}
ct(s) ^{- Obsolete Product(s 27.1.16}
Power management
The PSD module has bits in csiop registers that are configured at run-time by the 8032 to
reduce power consumption of the GPLD. The Turbo Bit in the PMMR0 register can be set to
logic ’1’ and both PLDs will go to Non-Turbo mode, meaning it will latch its outputs and go to
sleep until the next transition on its inputs. There is a slight penalty in PLD performance
(longer propagation delay), but significant power savings are realized. Going to Non-Turbo
mode may require an additional wait state in the 8032 SFR, BUSCON, because memory
decode signals are also delayed. The default state of the Turbo Bit is logic '0,' meaning by
default, the GPLD is in fast Turbo mode until the Turbo mode is turned off.
Additionally, bits in csiop registers PMMR0 and PMMR2 can be set by the 8032 to
selectively block signals from entering both PLDs which further reduces power
consumption. There is also an Automatic Power-down counter that detects lack of 8032
activity and reduces power consumption on the PSD module to its lowest level (see
Section 27.1.16: Power management on page 170).
Obsolete ^{Produ 27.1.17}
Security and NVM sector protection
A programmable security bit in the PSD module protects its contents from unauthorized
viewing and copying. The security bit is specified in PSDsoft Express and programmed into
the UPSD33xx with JTAG. Once set, the security bit will block access of JTAG programming
equipment to the PSD module Flash memory and PLD configuration, and also blocks JTAG
debugging access to the MCU module. The only way to defeat the security bit is to erase the
entire PSD module using JTAG (the erase command is the only JTAG command allowed
after the security bit has been set), after which the device is blank and may be used again.
Additionally and independently, the contents of each individual Flash memory sector can be
write protected (sector protection) by configuration with PSDsoft Express. This is typically
used to protect 8032 boot code from being corrupted by inadvertent WRITEs to Flash
memory from the 8032.
Status of sector protection bits may be read (but not written) using two registers in csiop
space.
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Doc ID 9685 Rev 7