UPSD3354DV-40U6 Datasheet, PDF (253/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
DC and AC parameters
Table 170. n, m, and x, y values
PSEN (code) cycle
# of PFQCLK in BUSCON register
n
m
3
1
2
4
2
3
5
3
4
6
4
5
7
-
-
READ cycle
n
m
-
-
2
3
3
4
4
5
5
6
WRITE cycle
x
y
-
-
2
1
3
2
4
3
5
4
Figure 88. External WRITE cycle (80-pin device only)
ALE
tLHLL
tWHLH
PSEN
ct(s) WR
Produ MCU
AD0 - AD7
lete _MCU
so ^{A8 - A11}
tAVLL
tLLWL
tLLAX
A0-A7
tAVWL
tWLWH
tWHQX
tQVWH
DATA OUT
A0-A7
INSTR IN
A8-A11
A8-A11
AI07877
- ^Ob _{Table 171. External WRITE cycle AC characteristics (3 V or 5 V device)}
ct(s) ^Symbol
Parameter
40 MHz oscillator⁽¹⁾
Variable oscillator
1/t_CLCL = 8 to 40 MHz
u _Min
Max
Min
Max
rod t_LHLL
P _tAVLL
te_tLLAX
ole ^tWLWH
s _tLLWL
Ob ^t_AVWL
ALE pulse width
Address Setup to ALE
Address hold after ALE
WR pulse width⁽²⁾
ALE to WR
Address valid to WR
17
13
7.5
40
7.5
27.5
t_CLCL – 8
t_CLCL – 12
0.5t_CLCL – 5
xt_CLCL – 10
0.5t_CLCL – 5
1.5t_CLCL – 10
Unit
ns
ns
ns
ns
ns
ns
t_WHLH
t_QVWH
WR high to ALE high
Data setup before WR^(y)
6.5
14.5 0.5t_CLCL – 6 0.5t_CLCL + 2 ns
20
yt_CLCL – 5
ns
t_WHQX Data hold after WR
6.5
14.5 0.5t_CLCL – 6 0.5t_CLCL + 2 ns
1. BUSCON register is configured for 4 PFQCLK.
2. Refer to Table 172 for “n” and “m” values.
Doc ID 9685 Rev 7
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