UPSD3354DV-40U6 Datasheet, PDF (258/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

DC and AC parameters
UPSD33xx
Table 178. CPLD macrocell asynchronous Clock mode timing (5 V PSD module)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate
Unit
Maximum frequency
external feedback
1/(t_SA+t_COA)
38.4
MHz
f_MAXA
Maximum frequency
internal feedback
(f_CNTA)
Maximum frequency
pipelined data
1/(t_SA+t_COA–10)
1/(t_CHA+t_CLA)
62.5
71.4
MHz
MHz
t_SA Input setup time
7
+ 2 + 10
ns
t_HA Input hold time
8
ns
t_CHA Clock input high time
9
+ 10
ns
t_CLA Clock input low time
9
) ^tCOA ^{Clock to output delay}
t(s ^{tARDA CPLD array delay}
Any macrocell
c _{tMINA Minimum clock period}
1/f_CNTA
16
+ 10
ns
21
+ 10 – 2 ns
11 + 2
ns
ns
rodu _{Table 179. CPLD macrocell asynchronous Clock mode timing (3timeV PSD module)}
te ^{P Symbol}
Parameter
Conditions
Min
Max
PT ^{Turbo Slew}
Aloc _{Off rate}
Unit
ole Maximum frequency
s _{external feedback}
1/(t_SA+t_COA)
ct(s) ^{- Ob fMAXA}
Maximum frequency
internal feedback
(f_CNTA)
Maximum frequency
pipelined data
1/(t_SA+t_COA–10)
1/(t_CHA+t_CLA)
du t_SA Input setup time
10
ro _{tHA Input hold time}
12
P _{tCHA Clock high time}
17
lete^{tCLA Clock low time}
13
o t_COA Clock to output delay
bs ^tARD ^{CPLD array delay}
Any macrocell
O _{tMINA Minimum clock period}
1/f_CNTA
36
21.7
MHz
27.8
MHz
33.3
MHz
+ 4 + 15
ns
ns
+ 15
ns
+ 15
ns
31
+ 15 – 6 ns
20 + 4
ns
ns
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Doc ID 9685 Rev 7