UPSD3354DV-40U6 Datasheet, PDF (198/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
27.4.27 General PLD (GPLD)
The GPLD is used to create general system logic. Figure 62 shows the architecture of the
entire GPLD, and Figure 64 shows the relationship between one OMC, one IMC, and one
I/O port pin, which is representative of pins on Ports A, B, and C. It is important to
understand how these elements work together. A more detailed description will follow for the
three major blocks (OMC, IMC, I/O Port) shown in Figure 64. Figure 64 also shows which
csiop registers to access for various PLD and I/O functions.
The GPLD contains:
● 16 Output Macrocells (OMC)
● 20 Input Macrocells (IMC)
● OMC Allocator
● Product Term Allocator inside each OMC
● AND-OR Array capable of generating up to 137 product terms
● Three I/O Ports, A, B, and C
Obsolete ^{Product(s) - Obsolete Product(s)}
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Doc ID 9685 Rev 7