UPSD3354DV-40U6 Datasheet, PDF (222/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
Figure 75. Port C structure
FROM AND-
OR ARRAY
FROM PLD
INPUT BUS
PT OUTPUT ENABLE, .OE (JTAG STATE MACHINE
AUTOMATICALLY CONTROLS OE FOR JTAG SIGNALS)
PSD MODULE RESET
Q ^DIRECTION
CSIOP
REGIS-
8032 ^TERS
DATA
Q
DRIVE
BITS _D
DRIVE TYPE SELECT⁽¹⁾
I/O PORT C
LOGIC
V_DD
PULL-UP
ONLY ON
50k _{JTAG TDI,}
TMS, TCK
SIGNALS
8032
WR
(MCUI/O)
PSDsoft
V_DD
V_DD
DATA OUT
Q
1^O
OUTPUT
U
ENABLE
TYPICAL
T
PIN,
CLR _RESET
P
U
) _{2 T}
t(s ³
c ₁ ^DIRECTION
4
M
U
u _{8032 P 2} DRIVE SELECT
5_X
d _{DATA D DATA OUT}
ro ^BIT
B _{3 (MCUI/O)}
P _{M 4} ^{ENABLE OUT}
U
te X ₅ DATA IN (MCUI/O)
bsole ^{8032 RD}
ONE of 6
CSIOP
REGISTERS
O FROM OMC
- ^ALLOCATOR
FROM OMC OUTPUT (MCELLBCx)
) FROM SRAM
t(s ^{BACK-UP CIRCUIT}
FROM FLASH MEMORIES
uc _{TO/FROM JTAG}
d _{STATE MACHINE}
STANDBY ON⁽¹⁾
RDY/BSY⁽¹⁾
TDO, TSTAT⁽¹⁾, TERR⁽¹⁾
TDI, TMS, TCK
TO IMCs
PIN
OUTPUT
PIN
CMOS _INPUT
BUFFER
NO
HYSTERESIS
IMCC2, IMCC3,
IMCC4, IMCC7
Pro 1. Optional function on a specific Port C pin.
PORT C
AI09181b
Obsolete ^27.4.50
Port D structure
Port D has two I/O pins (PD1, PD2) on 80-pin UPSD33xx devices, and just one pin (PD1) on
52-pin devices, supporting the following operating modes:
● MCU I/O mode
● DPLD Output mode for External Chip Selects, ECS1, ECS2. This does not consume
OMCs in the GPLD.
● PLD Input mode – direct input to the PLD Input Bus available to DPLD and GPLD. Does
not use IMCs
See Figure 76 on page 223 for detail.
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Doc ID 9685 Rev 7