UPSD3354DV-40U6 Datasheet, PDF (77/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
I/O ports of MCU module
17.1.1
GPIO function
Ports in GPIO mode operate as quasi-bidirectional pins, consistent with standard 8051
architecture. GPIO pins are individually controlled by three SFRs:
● SFR, P1 (Table 33 on page 80)
● SFR, P3 (Table 35 on page 81)
● SFR, P4 (Table 37 on page 81)
These SFRs can be accessed using the Bit Addressing mode, an efficient way to control
individual port pins.
17.1.2 GPIO output
Simply stated, when a logic '0' is written to a bit in any of these port SFRs while in GPIO
mode, the corresponding port pin will enable a low-side driver, which pulls the pin to ground,
and at the same time releases the high-side driver and pull-ups, resulting in a logic'0' output.
When a logic '1' is written to the SFR, the low-side driver is released, the high-side driver is
Obsolete ^{Product(s) - Obsolete Product(s) 17.1.3}
enabled for just one MCU_CLK period to rapidly make the 0-to1 transition on the pin, while
weak active pull-ups (total ~150 kOhms) to V_CC are enabled. This structure is consistent
with standard 8051 architecture. The high side driver is momentarily enabled only for 0-to-1
transitions, which is implemented with the delay function at the latch output as pictured in
Figure 16 through Figure 18 on page 80. After the high-side driver is disabled, the two weak
pull-ups remain enabled resulting in a logic '1' output at the pin, sourcing I_OH µA to an
external device. Optionally, an external pull-up resistor can be added if additional source
current is needed while outputting a logic '1.'
GPIO input
To use a GPIO port pin as an input, the low-side driver to ground must be disabled, or else
the true logic level being driven on the pin by an external device will be masked (always
reads logic '0'). So to make a port pin “input ready”, the corresponding bit in the SFR must
have been set to a logic '1' prior to reading that SFR bit as an input. A reset condition forces
SFRs P1, P3, and P4 to FFh, thus all three ports are input ready after reset.
When a pin is used as an input, the stronger pull-up “A” maintains a solid logic '1' until an
external device drives the input pin low. At this time, pull-up “A” is automatically disabled,
and only pull-up “B” will source the external device I_IH µA, consistent with standard 8051
architecture.
GPIO bi-directional
It is possible to operate individual port pins in bi-directional mode. For an output, firmware
would simply write the corresponding SFR bit to logic '1' or '0' as needed. But before using
the pin as an input, firmware must first ensure that a logic '1' was the last value written to the
corresponding SFR bit prior to reading that SFR bit as an input.
GPIO current capability
A GPIO pin on Port 4 can sink twice as much current than a pin on either Port 1 or Port 3
when the low-side driver is outputting a logic '0' (I_OL). See the DC specifications at the end
of this document for full details.
Doc ID 9685 Rev 7
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