UPSD3354DV-40U6 Datasheet, PDF (225/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
no PLD inputs are changing, and the PLDs will even use less AC current when inputs do
change compared to Turbo mode.
When the Turbo mode is enabled, there is a significant DC current component AND the
AC current component is higher than non-Turbo mode, as shown in Figure 84 on
page 242 (5 V) and Figure 85 on page 243 (3.3 V).
Blocking bits
Significant power savings can be achieved by blocking 8032 bus control signals (RD, WR,
PSEN, ALE) from reaching PLD inputs, if these signals are not used in any PLD equations.
Blocking is achieved by the 8032 writing to the “blocking bits” in csiop PMMR registers.
Current consumption of the PLDs is directly related to the composite frequency of all
transitions on PLD inputs, so blocking certain PLD inputs can significantly lower PLD
operating frequency and power consumption (resulting in a lower frequency on the graphs of
Figure 84 on page 242 and Figure 85 on page 243).
Note:
It is recommended to prevent unused inputs from floating on Ports A, B, C, and D by pulling
them up to V_DD with a weak external resistor (100 KΩ), or by setting the csiop Direction
register to “output” at run-time for all unused inputs. This will prevent the CMOS input buffers
) ^{of unused input pins from drawing excessive current.}
t(s ^{The csiop PMMR register definitions are shown in Table 154 through Table 156 on}
c page 226.
du _{Table 154. Power Management Mode register PMMR0 (address = csiop + offset B0h)(1)}
ro _Bit
P _num.
Bit name Value
Description
lete ^{Bit 0}
X
0 Not used, and should be set to zero.
bso ^{Bit 1 APD Enable}
0 Automatic Power-down (APD) counter is disabled.
1 APD counter is enabled
- ^{O Bit 2}
X
0 Not used, and should be set to zero.
t(s) ^{Bit 3}
roduc ^{Bit 4}
Obsolete ^{P Bit 5}
PLD Turbo
Disable
0 = on PLD Turbo mode is on
1 = off PLD Turbo mode is off, saving power.
Blocking bit,
CLKIN to
PLDs⁽²⁾
0 = on
CLKIN (pin PD1) to the PLD Input Bus is not blocked. Every transition of CLKIN
powers-up the PLDs.
1 = off
CLKIN input to PLD Input Bus is blocked, saving power. But CLKIN still goes to
APD counter.
Blocking bit,
CLKIN to
OMCs only⁽²⁾
0 = on
1 = off
CLKIN input is not blocked from reaching all OMC’s common clock inputs.
CLKIN input to common clock of all OMCs is blocked, saving power. But CLKIN
still goes to APD counter and all PLD logic besides the common clock input on
OMCs.
Bit 6
X
0 Not used, and should be set to zero.
Bit 7
X
0 Not used, and should be set to zero.
1. All the bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the
registers.
2. Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation.
Doc ID 9685 Rev 7
225/272