UPSD3354DV-40U6 Datasheet, PDF (235/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
Figure 79. JTAG chain in UPSD33xx package
OPTIONAL
DEBUG
RESET_IN
MCU MODULE
UPSD33XX
8032 MCU
RESET
JTAG TAP
CONTROLLER
TDO TMS TCK TDI
JTAG TDO
JTAG TCK
IEEE 1149.1
JTAG TMS
JTAG TDI
Obsolete ^{Product(s) - Obsolete Product(s) 27.5.3}
PC3 / TSTAT
OPTIONAL
PC4 / TERR
TDI
TSTAT
TERR
TMS TCK TDO
JTAG TAP
CONTROLLER
RST
MAIN
2ND
FLASH FLASH PLD
MEMORY MEMORY
PSD MODULE
AI09184b
In-system programming
The ISP function can use two different configurations of the JTAG interface:
● 4-pin JTAG: TDI, TDO, TCK, TMS
● 6-pin JTAG: Signals above plus TSTAT, TERR
At power-up, the four basic JTAG signals are all inputs, waiting for a command to appear on
the JTAG bus from programming or test equipment. When the enabling command is
received, TDO becomes an output and the JTAG channel is fully functional. The same
command that enables the JTAG channel may optionally enable the two additional signals,
TSTAT and TERR.
Doc ID 9685 Rev 7
235/272