UPSD3354DV-40U6 Datasheet, PDF(33/272 Page) STMicroelectronics – fast 8032 MCU with programmable logic

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UPSD3354DV-40U6 Datasheet, PDF (33/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

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UPSD33xx

8032 MCU core performance enhancements

Figure 7. Instruction pre-fetch queue and branch cache

Branch

Cache

(BC)

Branch 4 Branch 4 Branch 4 Branch 4 Branch 4 Branch 4

Code

Code

Code

Code

Code

Code

Previous

Branch 4

Branch 3 Branch 3 Branch 3 Branch 3 Branch 3 Branch 3

Code

Code

Code

Code

Code

Code

Previous

Branch 3

Branch 2 Branch 2 Branch 2 Branch 2 Branch 2 Branch 2

Code

Code

Code

Code

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Previous

Branch 2

Branch 1 Branch 1 Branch 1 Branch 1 Branch 1 Branch 1

Code

Code

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Branch 1

Address

Compare

Load on Branch Address Match

Current

Branch

Address

Instruction

Instruction

Byte

Byte

8032

Program

Memory on

t(s) PSD Module

8

Address

16

duc Wait

6 Bytes of Instruction

Instruction Pre-Fetch Queue (PFQ)

8

Address

16

Stall

MCU

AI08809

te Pro 5.1

Pre-Fetch Queue (PFQ) and Branch Cache (BC)

ole The PFQ is always working to minimize the idle bus time inherent to 8032 MCU architecture,

s to eliminate wasted memory fetches, and to maximize memory bandwidth to the MCU. The

b PFQ does this by running asynchronously in relation to the MCU, looking ahead to pre-fetch

O code from program memory during any idle bus periods. Only necessary bytes will be

- fetched (no dummy fetches like standard 8032). The PFQ will queue up to six code bytes in

) advance of execution, which significantly optimizes sequential program performance.

t(s However, when program execution becomes non-sequential (program branch), a typical pre-

c fetch queue will empty itself and reload new code, causing the MCU to stall. The Turbo

u UPSD33xx diminishes this problem by using a Branch Cache with the PFQ. The BC is a

d four-way, fully associative cache, meaning that when a program branch occurs, it's branch

ro destination address is compared simultaneously with four recent previous branch

P destinations stored in the BC. Each of the four cache entries contain up to six bytes of code

terelated to a branch. If there is a hit (a match), then all six code bytes of the matching

leprogram branch are transferred immediately and simultaneously from the BC to the PFQ,

and execution on that branch continues with minimal delay. This greatly reduces the chance

so that the MCU will stall from an empty PFQ, and improves performance in embedded control

Ob systems where it is quite common to branch and loop in relatively small code localities.

By default, the PFQ and BC are enabled after power-up or reset. The 8032 can disable the

PFQ and BC at runtime if desired by writing to a specific SFR (BUSCON).

The memory in the PSD module operates with variable wait states depending on the value

specified in the SFR named BUSCON. For example, a 5 V UPSD33xx device operating at a

40 MHz crystal frequency requires four memory wait states (equal to four MCU clocks). In

this example, once the PFQ has one or more bytes of code, the wait states become

Doc ID 9685 Rev 7

33/272

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