UPSD3354DV-40U6 Datasheet, PDF (70/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Power saving modes
15 Power saving modes
UPSD33xx
The UPSD33xx is a combination of two die, or modules, each module having it’s own
current consumption characteristics. This section describes reduced power modes for the
MCU module. See Section 27.1.16: Power management on page 170 for reduced power
modes of the PSD module. Total current consumption for the combined modules is
determined in the DC specifications at the end of this document.
The MCU module has three software-selectable modes of reduced power operation.
● Idle mode
● Power-down mode
● Reduced Frequency mode
15.1 Idle mode
Idle mode will halt the 8032 MCU core while leaving the MCU peripherals active (Idle mode
) _{blocks MCU_CLK only). For lowest current consumption in this mode, it is recommended to}
t(s ^{disable all unused peripherals, before entering Idle mode (such as the ADC and the debug}
c ^{unit breakpoint comparators). The following functions remain fully active during Idle mode}
u (except if disabled by SFR settings).
d _{● External Interrupts INT0 and INT1}
ro _{● Timer 0, Timer 1 and Timer 2}
P _{● Supervisor reset from: LVD, JTAG debug, external RESET_IN_, but not the WTD}
te _{● ADC}
le _{● I2C Interface}
so _{● UART0 and UART1 Interfaces}
b _{● SPI Interface}
- ^O ● Programmable Counter Array
t(s) ^{An interrupt generated by any of these peripherals, or a reset generated from the}
supervisor, will cause Idle mode to exit and the 8032 MCU will resume normal operation.
uc The output state on I/O pins of MCU ports 1, 3, and 4 remain unchanged during Idle mode.
rod ^{To enter Idle mode, the 8032 MCU executes an instruction to set the IDL bit in the SFR}
named PCON, shown in Table 31 on page 72. This is the last instruction executed in normal
P _{operating mode before Idle mode is activated. Once in Idle mode, the MCU status is entirely}
te^{preserved, and there are no changes to: SP, PSW, PC, ACC, SFRs, DATA, IDATA, or XDATA.}
le_{The following are factors related to Idle mode exit:}
so ^{● Activation of any enabled interrupt will cause the IDL bit to be cleared by hardware,}
b _{terminating Idle mode. The interrupt is serviced, and following the Return from Interrupt}
O instruction (RETI), the next instruction to be executed will be the one which follows the
instruction that set the IDL bit in the PCON SFR.
● After a reset from the supervisor, the IDL bit is cleared, Idle mode is terminated, and
the MCU restarts after three MCU machine cycles.
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Doc ID 9685 Rev 7