UPSD3354DV-40U6 Datasheet, PDF (234/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
module (Flash memory and PLD) may be programmed with JTAG ISP, but only the Flash
memories may be programmed using IAP.
27.5.2 JTAG chaining inside the package
JTAG protocol allows serial “chaining” of more than one device in a JTAG chain. The
UPSD33xx is assembled with a stacked die process combining the PSD module (one die)
and the MCU module (the other die). These two die are chained together within the
UPSD33xx package. The standard JTAG interface has four basic signals:
● TDI - Serial data into device
● TDO - Serial data out of device
● TCK - Common clock
● TMS - mode Selection
Every device that supports IEEE 1149.1 JTAG communication contains a Test Access Port
(TAP) controller, which is a small state machine to manage JTAG protocol and serial
streams of commands and data. Both the PSD module and the MCU module each contain a
TAP controller.
t(s) ^{Figure 79 on page 235 illustrates how these die are chained within a package. JTAG}
programming/test equipment will connect externally to the four IEEE 1149.1 JTAG pins on
c _{Port C. The TDI pin on the UPSD33xx package goes directly to the PSD module first, then}
u _{exits the PSD module through TDO. TDO of the PSD module is connected to TDI of the}
rod ^{MCU module. The serial path is completed when TDO of the MCU module exits the}
UPSD33xx package through the TDO pin on Port C. The JTAG signals TCK and TMS are
P _{common to both modules as specified in IEEE 1149.1. When JTAG devices are chained,}
te ^{typically one devices is in BYPASS mode while another device is executing a JTAG}
le ^{operation. For the UPSD33xx, the PSD module is in BYPASS mode while debugging the}
o ^{MCU module, and the MCU module is in BYPASS mode while performing ISP on the PSD}
s _module.
b _{The RESET_IN input pin on the UPSD33xx package goes to the MCU module, and this}
- ^{O module will generate the RST reset signal for the PSD module. These reset signals are}
) totally independent of the JTAG TAP controllers, meaning that the JTAG channel is
t(s ^{operational when the modules are held in reset. It is required to assert RESET_IN during}
ISP. STMicroelectronics and 3rd party JTAG ISP tools will automatically assert a reset signal
uc ^{during ISP. However, this reset signal must be connected to RESET_IN as shown in}
Obsolete ^{Prod examples in Figure 80 and Figure 81 on page 238.}
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Doc ID 9685 Rev 7