UPSD3354DV-40U6 Datasheet, PDF (178/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
Table 115. VM register (address = csiop + offset E2h)⁽¹⁾⁽²⁾
Bit 7
PIO_EN
Bit 6
Bit 5
Bit 4
Main Flash
XDATA
space
Bit 3
Secondary
Flash
XDATA
space
Bit 2
Main Flash
Program
space
Bit 1
Secondary
Flash
Program
space
Bit 0
SRAM Program space
0 = disable
Peripheral
I/O mode on
Port A
not
used
1 = enable
Peripheral
I/O mode on
Port A
not
used
not
used
not
used
0 = RD or
WR cannot
access
main Flash
0 = RD or
WR cannot
access
secondary
Flash
0 = PSEN
cannot
access
main Flash
0 = PSEN
cannot
access
secondary
Flash
0 = PSEN cannot access
SRAM
1 = RD or
WR can
access
main Flash
1 = RD or
WR can
access
secondary
Flash
1 = PSEN
can access
Main Flash
1 = PSEN
can access
secondary
Flash
1 = PSEN can access
SRAM
1. Default value of Bits 0, 1, 2, 3, and 4 is loaded from Non-Volatile setting as specified from PSDsoft Express upon any reset
or power-up condition. The default value of these bits can be overridden by 8032 at run-time.
Obsolete ^{Product(s) - Obsolete Product(s) 2. Default value of Bit 7 is zero upon any reset condition.}
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Doc ID 9685 Rev 7