UPSD3354DV-40U6 Datasheet, PDF (147/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Synchronous peripheral interface (SPI)
Table 85.
Bit 7
–
SPICON0: Control register 0 (SFR D6h, Reset Value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TE
RE
SPIEN
SSEL
FLSB
SBO
Bit 0
–
Table 86. SPICON0 register bit definition
Bit
Symbol
R/W
Definition
7
–
–
Reserved
Transmitter Enable
6
TE
RW 0 = Transmitter is disabled
1 = Transmitter is enabled
Receiver Enable
5
RE
RW 0 = Receiver is disabled
1 = Receiver is enabled
SPI Enable
) 4
SPIEN
RW 0 = Entire SPI Interface is disabled
t(s ^{1 = Entire SPI Interface is enabled}
c _{Slave Selection}
u _{0 = SPISEL output pin is constant logic '1' (slave device not}
rod ³
SSEL
RW selected)
1 = SPISEL output pin is logic '0' (slave device is selected)
P _{during data transfers}
te _{First LSB}
le ₂
FLSB
RW 0 = Transfer the most significant bit (MSB) first
o _{1 = Transfer the least significant bit (LSB) first}
bs _{Sampling Polarity}
O _{0 = Sample transfer data at the falling edge of clock (SPICLK}
- ₁
SPO
–
is '0' when idle)
t(s) 1 = Sample transfer data at the rising edge of clock (SPICLK is
'1' when idle)
Obsolete ^{Produc 0}
–
–
Reserved
Doc ID 9685 Rev 7
147/272