UPSD3354DV-40U6 Datasheet, PDF (180/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
Figure 59. VM register example corresponding to memory map example of Figure 32
8032 Address
53 Other PLD Inputs
DPLD
RS0
CSBOOT0 - CSBOOT3
FS0 - FS7
Main Flash
Memory
CS
WR OE
CS
Secondary
Flash
Memory
WR OE
CS
SRAM
WR OE
VM Register = 0Ch
PSEN
WR
RD
AI02869D
Product(s) ^27.3
Runtime control register definitions (CSIOP)
The 39 csiop registers are defined in Table 116. The 8032 can access each register by the
address offset (specified in Table 116) added to the csiop base address that was specified
in PSDsoft Express. Do not write to unused locations within the csiop block of 256 registers,
they should remain logic zero.
lete _{Table 116. CSIOP registers and their Offsets (in hexadecimal}
bso ^Register
O ^name
Port A
(80-
pin)
Port B
Port C
Port D
Other
Description
Link
t(s) ^{- Data In}
00h
01h
10h
11h
MCU I/O input mode. Read to obtain Table 132
current logic level of pins on Ports A, B,
on
C, or D. No WRITEs.
page 210
Produc ^Control
02h
03h
Selects MCUI/O or Latched Address
Out mode. Logic 0 = MCU I/O, 1 =
8032 Addr Out. Write to select mode.
Read for status.
Table 144
on
page 214
bsolete ^{Data Out}
04h
05h
12h
13h
MCU I/O output mode. Write to set
logic level on pins of Ports A, B, C, or
D. Read to check status. This register
has no effect if a port pin is driven by
an OMC output from PLD.
Table 136
on
page 210
O _{MCU I/O mode. Configures port pin as}
input or output. Write to set direction of _{Table 140}
Direction
06h
07h
14h
15h
port pins.
on
Logic 1 = out, Logic 0 = in. Read to
page 211
check status.
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Doc ID 9685 Rev 7