UPSD3354DV-40U6 Datasheet, PDF (152/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Analog-to-digital converter (ADC)
UPSD33xx
Table 94. ACON register bit definition (continued)
Bit
Symbol
Function
Analog channel Select
000 Select channel 0 (P1.0)
001 Select channel 0 (P1.1)
010 Select channel 0 (P1.2)
4..2
ADS2.. 0
011 Select channel 0 (P1.3)
101 Select channel 0 (P1.5)
110 Select channel 0 (P1.6)
111 Select channel 0 (P1.7)
ADC Start Bit
1
ADST
0 = Force to zero
1 = Start ADC, then after one cycle, the bit is
cleared to '0.'
ADC Status Bit
0
ADSF
0 = ADC conversion is not completed
) _{1 = ADC conversion is completed. The bit can}
t(s ^{also be cleared with software.}
duc Table 95. ADCPS register bit definition (SFR 94h, Reset Value 00h)
ro _Bit
Symbol
Function
P _7:4
–
Reserved
te _{ADC Conversion Reference Clock Enable}
le ₃
ADCCE 0 = ADC reference clock is disabled (default)
so 1 = ADC reference clock is enabled
b _{ADC Reference Clock PreScaler}
O _{Only three Prescaler values are allowed:}
) ^- ADCPS[2:0] = 0, for f_OSC frequency 16 MHz or less. Resulting ADC clock
t(s ^2:0
ADCPS[2:0] ^{is fOSC.}
c^{ADCPS[2:0] = 1, for fOSC frequency 32 MHz or less. Resulting ADC clock}
u ^{is f}OSC^/2.
d ADCPS[2:0] = 2, for f_OSC frequency 32 MHz > 40 MHz. Resulting ADC
ro ^{clock is fOSC/4.}
te ^P Table 96.
le _Bit
Obso ^7:0
ADAT0 register (SFR 95H, Reset Value 00h)
Symbol
Function
–
Store ADC output, Bit 7 - 0
Table 97. ADAT1 register (SFR 96h, Reset Value 00h)
Bit
Symbol
Function
7:2
–
Reserved
1.. 0
–
Store ADC output, Bit 9, 8
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Doc ID 9685 Rev 7