UPSD3354DV-40U6 Datasheet, PDF (171/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
27.2
Memory mapping
There many different ways to place (or map) the address range of PSD module memory and
I/O depending on system requirements. The DPLD provides complete mapping flexibility.
Figure 52 shows one possible system memory map. In this example, 128 Kbytes of main
Flash memory for a UPSD3333 device is in 8032 program address space, and 32 Kbytes of
secondary Flash memory, the SRAM, and csiop registers are all in 8032 XDATA space.
In Figure 52, the nomenclature fs0..fs7 are designators for the individual sectors of main
Flash memory, 16 Kbytes each. CSBOOT0..CSBOOT3 are designators for the individual
secondary Flash memory segments, 8 Kbytes each. rs0 is the designator for SRAM, and
csiop designates the PSD module control register set.
The designer may easily specify memory mapping in a point-and-click software environment
using PSDsoft Express, creating a non-volatile configuration when the DPLD is
programmed using JTAG.
27.2.1 8032 program address space
Obsolete ^{Product(s) - Obsolete Product(s) 27.2.2}
In the example of Figure 52, six sectors of main Flash memory (fs2.. fs7) are paged across
three memory pages in the upper half of program address space, and the remaining two
sectors of main Flash memory (fs0, fs1) reside in the lower half of program address space,
and these two sectors are independent of paging (they reside in “common” program address
space). This paged memory example is quite common and supported by many 8051
software compilers.
8032 data address space (XDATA)
Four sectors of secondary Flash memory reside in the upper half of 8032 XDATA space in
the example of Figure 52. SRAM and csiop registers are in the lower half of XDATA space.
The 8032 SFR registers and local SRAM inside the 8032 MCU module do not reside in
XDATA space, so it is OK to place PSD module SRAM or csiop registers at an address that
overlaps the address of internal 8032 MCU module SRAM and registers.
Figure 52. Typical system memory map
8032 PROGRAM SPACE
(PSEN)
Page 0 Page 1 Page 2
FFFFh
fs3
16KB
C000h
fs5
16KB
fs7
16KB
8000h
fs2
16KB
fs4
16KB
fs6
16KB
8032 XDATA
SPACE
(RD and WR)
Page X
csboot3
8KB
FFFFh
E000h
csboot2
8KB _C000h
csboot1
8KB
csboot0
8KB
A000h
8000h
fs1, 16KB
Common Memory to All Pages
System
I/O
4000h
fs0, 16KB
Common Memory to All Pages
0000h
csiop
256B 2000h
rs0, 8KB
0000h
AI09173
Doc ID 9685 Rev 7
171/272