UPSD3354DV-40U6 Datasheet, PDF (231/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
the DC component (y-axis crossing), the user can calculate the number by multiplying the
number of product terms used (from fitter report) times the DC current per product term
specified in the DC specifications for the PSD module. The total PLD current usage is the
sum of its AC and DC components.
27.4.58 Non-turbo mode current consumption
Notice in Figure 84 and Figure 85 on page 243 that when Turbo mode is off, the DC current
consumption is “zero” (just standby current) when the composite frequency of PLD input
transitions is zero (no input transitions). Now moving up the frequency axis to consider the
AC current component, current consumption remains considerably less than Turbo mode
until PLD input transitions happen so rapidly that the PLDs do not have time to latch their
outputs and go to standby between the transitions anymore. This is where the lines
converge on the graphs, and current consumption becomes the same for PLD input
transitions at this frequency and higher regardless if Turbo mode is on or off. To determine
the current consumption of the PLDs with Turbo mode off, extrapolate the AC component
from the graph based on number of product terms and input frequency. The only DC
component in non-Turbo mode is the PSD module standby current.
) The key to reducing PLD current consumption is to reduce the composite frequency of
t(s ^{transitions on the PLD input bus, moving down the frequency scale on the graphs. One way}
to do this is to carefully select which signals are entering PLD inputs, not selecting high
uc frequency signals if they are not used in PLD equations. Another way is to use PLD
d _{“Blocking Bits” to block certain signals from entering the PLD input bus.}
olete ^{Pro 27.4.59}
PLD blocking bits
Blocking specific signals from entering the PLDs using bits of the csiop PMMR registers can
further reduce PLD AC current consumption by lowering the effective composite frequency
of inputs to the PLDs.
Obsolete ^{Product(s) - Obs 27.4.60}
Blocking 8032 bus control signals
When the 8032 is active on the MCU module, four bus control signals (RD, WR, PSEN, and
ALE) are constantly transitioning to manage 8032 bus traffic. Each time one of these signals
has a transition from logic ’1’ to '0,' or 0 to '1,' it will wake up the PLDs if operating in non-
Turbo mode, or when in Turbo mode it will cause the affected PLD gates to draw current. If
equations in the DPLD or GPLD do not use the signals RD, WR, PSEN, or ALE then these
signals can be blocked which will reduce the AC current component substantially. These bus
control signals are rarely used in DPLD equations because they are routed in silicon directly
to the memory arrays of the PSD module, bypassing the PLDs. For example, it is NOT
necessary to qualify a memory chip select signal with an MCU write strobe, such as “fs0 =
address range & !WR_”. Only “fs0 = address range” is needed.
Each of the 8032 bus control signals may be blocked individually by writing to Bits 2, 3, 4,
and 5 of the PMMR2 register shown in Table 155 on page 226. Blocking any of these four
bus control signals only prevents them from reaching the PLDs, but they will always go to
the memories directly.
However, sometimes it is necessary to use these 8032 bus control signals in the GPLD
when creating interface signals to external I/O peripherals. But it is still possible to save
power by dynamically unblocking the bus signals before reading/writing the external device,
then blocking the signals after the communication is complete.
Doc ID 9685 Rev 7
231/272