UPSD3354DV-40U6 Datasheet, PDF (151/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Figure 45. 10-Bit ADC
AVREF
AVREF
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ANALOG
MUX
SELECT
Analog-to-digital converter (ADC)
10-BIT SAR ADC
CONTROL
ADC OUT - 10 BITS
ADAT1
ACON REG
REG
ADAT 0 REG
AI07856
t(s) _{Table 93.}
uc _{Bit 7}
rod ^AINTF
ACON register (SFR 97h, Reset Value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
AINTEN ADEN
ADS2
ADS1
ADS0
Bit 1
ADST
Bit 0
ADSF
te ^P _{Table 94. ACON register bit definition}
le _Bit
Symbol
- ^Obso ₇
AINTF
duct(s) ₆
AINTEN
Obsolete ^Pro5
ADEN
Function
ADC Interrupt flag. This bit must be cleared with
software.
0 = No interrupt request
1 = The AINTF flag is set when ADSF goes from
'0' to '1.' Interrupts CPU when both AINTF and
AINTEN are set to '1.'
ADC Interrupt Enable
0 = ADC interrupt is disabled
1 = ADC interrupt is enabled
ADC Enable Bit
0 = ADC shut off and consumes no operating
current
1 = Enable ADC. After ADC is enabled, 16ms of
calibration is needed before ADST Bit is set.
Doc ID 9685 Rev 7
151/272