UPSD3354DV-40U6 Datasheet, PDF (263/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
DC and AC parameters
Figure 96. ISC timing
t_ISCCH
TCK
t _ISCCL
t _ISCPSU t_ISCPH
TDI/TMS
t _ISCPZV
t _ISCPCO
ISC OUTPUTS/TDO
t_ISCPVZ
) ^{ISC OUTPUTS/TDO}
duct(s _{Table 188. ISC timing (5 V PSD module)}
ro _Symbol
Parameter
Conditions Min
te ^{P tISCCF Clock (TCK, PC1) frequency (except for PLD)}
(1)
le ^{tISCCH Clock (TCK, PC1) high time (except for PLD)}
(1)
23
o _{tISCCL Clock (TCK, PC1) low time (except for PLD)}
(1)
23
bs _{tISCCFP Clock (TCK, PC1) frequency (PLD only)}
(2)
O _{tISCCHP Clock (TCK, PC1) high time (PLD only)}
(2)
90
) ^- _{tISCCLP Clock (TCK, PC1) low time (PLD only)}
(2)
90
t(s ^t_ISCPSU ^{ISC Port setup time}
7
uc ^tISCPH ^{ISC Port hold up time}
5
d _{tISCPCO ISC Port clock to output}
ro _{tISCPZV ISC Port high-impedance to valid output}
te ^{P tISCPVZ ISC Port valid output to high-impedance}
le^{1. For non-PLD Programming, Erase or in ISC By-pass mode.}
Obso ^{2. For Program or Erase PLD only.}
AI02865
Max Unit
20 MHz
ns
ns
4 MHz
ns
ns
ns
ns
21
ns
21
ns
21
ns
Doc ID 9685 Rev 7
263/272