UPSD3354DV-40U6 Datasheet, PDF (169/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
27.1.14
I/O ports
For 80-pin UPSD33xx devices, the PSD module has 22 individually configurable I/O pins
distributed over four ports (these I/O are in addition to I/O on MCU module). For 52-pin
UPSD33xx devices, the PSD module has 13 individually configurable I/O pins distributed
over three ports. See Figure 73 on page 219 for I/O port pin availability on these two
packages.
I/O port pins on the PSD module (Ports A, B, C, and D) are completely separate from the
port pins on the MCU module (Ports 1, 3, and 4). They even have different electrical
characteristics. I/O port pins on the PSD module are accessed by csiop registers, or they
are controlled by PLD equations. Conversely, I/O Port pins on the MCU module are
controlled by the 8032 SFR registers.
Table 113. General I/O pins on PSD module
Pkg
Port A
Port B
Port D
Port D
Total
52-pin
0
8
4
1
13
Obsolete ^{Product(s) - Obsolete Product(s) Note:}
80-pin
8
8
4
2
22
Four pins on Port C are dedicated to JTAG, leaving four pins for general I/O.
Each I/O pin on the PSD module can be individually configured for different functions on a
pin-by-pin basis (Figure 68 on page 208). Following are the available functions on PSD
module I/O pins.
● MCU I/O: 8032 controls the output state of each port pin or it reads input state of each
port pin, by accessing csiop registers at run-time. The direction (in or out) of each pin is
also controlled by csiop registers at run-time.
● PLD I/O: PSDsoft Express logic equations and pin configuration selections determine if
pins are connected to OMC outputs or IMC inputs. This is a static and non-volatile
configuration. Port pins connected to PLD outputs can no longer be driven by the 8032
using MCU I/O output mode.
● Latched MCU Address Output: Port A or Port B can output de-multiplexed 8032
address signals A0 - A7 on a pin-by-pin basis as specified in csiop registers at run-
time. In addition, Port B can also be configured to output de-multiplexed A8-A15 in
PSDsoft Express.
● Data Bus Repeater: Port A can bi-directionally buffer the 8032 data bus (de-
multiplexed) for a specified address range in PSDsoft Express. This is referred to as
Peripheral I/O mode in this document.
● Open Drain Outputs: Some port pins can function as open-drain as specified in csiop
registers at run-time.
● Pins on Port D can be used for external chip-select outputs originating from the
DPLD, without consuming OMC resources within the GPLD.
Doc ID 9685 Rev 7
169/272