UPSD3354DV-40U6 Datasheet, PDF (55/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
UPSD33xx instruction set summary
Table 10.
Program branching instruction set (continued)
Mnemonic⁽¹⁾
and use
Description
Length/cycles
CJNE
Rn, #data, rel
Compare immediate to
register, jump if not
equal
CJNE
@Ri, #data, rel
Compare immediate to
indirect, jump if not
equal
DJNZ
Rn, rel
Decrement register and
jump if not zero
DJNZ
direct, rel
Decrement direct byte
and jump if not zero
1. All mnemonics copyrighted ©Intel Corporation 1980.
3 byte/2 cycle
3 byte/2 cycle
2 byte/2 cycle
3 byte/2 cycle
t(s) ^{Table 11.}
Miscellaneous instruction set
Mnemonic⁽¹⁾
and use
Description
uc _NOP
No operation
rod ^{1. All mnemonics copyrighted ©Intel Corporation 1980.}
Length/cycles
1 byte/1 cycle
te ^{P Table 12. Notes on instruction set and addressing modes}
le ^{Rn Register R0 - R7 of the currently selected register bank.}
bso ^direct
8-bit address for internal 8032 DATA SRAM (locations 00h - 7Fh) or SFR registers
(locations 80h - FFh).
- ^{O @Ri}
8-bit internal 8032 SRAM (locations 00h - FFh) addressed indirectly through contents of
R0 or R1.
t(s) ^{#data 8-bit constant included within the instruction.}
c ^{#data16 16-bit constant included within the instruction.}
u _{addr16 16-bit destination address used by LCALL and LJMP.}
rod ^{addr11 11-bit destination address used by ACALL and AJMP.}
P _{rel Signed (two-s compliment) 8-bit offset byte.}
Obsolete^bit
Direct addressed bit in internal 8032 DATA SRAM (locations 20h to 2Fh) or in SFR
registers (88h, 90h, 98h, A8h, B0, B8h, C0h, C8h, D0h, D8h, E0h, F0h).
Doc ID 9685 Rev 7
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