UPSD3354DV-40U6 Datasheet, PDF (123/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
I²C interface
23.2 Communication flow
I²C data flow control is based on the fact that all I²C compatible devices will drive the bus
lines with open-drain (or open-collector) line drivers pulled up with external resistors,
creating a wired-AND situation. This means that either bus line (SDA or SCL) will be at a
logic '1' level only when no I²C device is actively driving the line to logic '0.' The logic for
handshaking, arbitration, synchronization, and collision detection is implemented by each
I²C device having:
1. The ability to hold a line low against the will of the other devices who are trying to
assert the line high.
2. The ability of a device to detect that another device is driving the line low against its will.
Assert high means the driver releases the line and external pull-ups passively raise the
signal to logic '1.' Holding low means the open-drain driver is actively pulling the signal to
ground for a logic '0.'
For example, if a Slave device cannot transmit or receive a byte because it is distracted by
and interrupt or it has to wait for some process to complete, it can hold the SCL clock line
low. Even though the Master device is generating the SCL clock, the Master will sense that
) the Slave is holding the SCL line low against the will of the Master, indicating that the Master
t(s ^{must wait until the Slave releases SCL before proceeding with the transfer.}
c _{Another example is when two Master devices try to put information on the bus}
u _{simultaneously, the first one to release the SDA data line looses arbitration while the winner}
rod ^{continues to hold SDA low.}
P ^{Two types of data transfers are possible with I2C depending on the R/W bit, see Figure 38}
on page 124.
te _{1. Data transfer from Master Transmitter to Slave Receiver (R/W = 0). In this case, the}
le _{Master generates a START condition on the bus and it generates a clock signal on the}
so ^{SCL line. Then the Master transmits the first byte on the SDA line containing the 7-bit}
b _{Slave address plus the R/W bit. The Slave who owns that address will respond with an}
O acknowledge bit on SDA, and all other Slave devices will not respond. Next, the Master
- _{will transmit a data byte (or bytes) that the addressed Slave must receive. The Slave}
) _{will return an acknowledge bit after each data byte it successfully receives. After the}
t(s ^{final byte is transmitted by the Master, the Master will generate a STOP condition on}
c ^{the bus, or it will generate a RE-START condition and begin the next transfer. There is}
u _{no limit to the number of bytes that can be transmitted during a transfer session.}
d _{2. Data transfer from Slave Transmitter to Master Receiver (R/W = 1). In this case, the}
ro _{Master generates a START condition on the bus and it generates a clock signal on the}
P _{SCL line. Then the Master transmits the first byte on the SDA line containing the 7-bit}
te^{Slave address plus the R/W bit. The Slave who owns that address will respond with an}
le ^{acknowledge bit on SDA, and all other Slave devices will not respond. Next, the}
o ^{addressed Slave will transmit a data byte (or bytes) to the Master. The Master will}
s return an acknowledge bit after each data byte it successfully receives, unless it is the
b _{last byte the Master desires. If so, the Master will not acknowledge the last byte and}
O _{from this, the Slave knows to stop transmitting data bytes to the Master. The Master will}
then generate a STOP condition on the bus, or it will generate a RE-START condition
and begin the next transfer. There is no limit to the number of bytes that can be
transmitted during a transfer session.
Doc ID 9685 Rev 7
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