UPSD3354DV-40U6 Datasheet, PDF (26/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx hardware description
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UPSD33xx hardware description
UPSD33xx
The UPSD33xx has a modular architecture built from a stacked die process. There are two
die, one is designated “MCU module” in this document, and the other is designated “PSD
module” (see Figure 4 on page 27). In all cases, the MCU module die operates at 3.3 V with
5 V tolerant I/O. The PSD module is either a 3.3 V die or a 5 V die, depending on the
UPSD33xx device as described below.
The MCU module consists of a fast 8032 core, that operates with 4 clocks per instruction
cycle, and has many peripheral and system supervisor functions. The PSD module provides
the 8032 with multiple memories (two Flash and one SRAM) for program and data,
programmable logic for address decoding and for general-purpose logic, and additional I/O.
The MCU module communicates with the PSD module through internal address and data
busses (A8 – A15, AD0 – AD7) and control signals (RD, WR, PSEN, ALE, RESET).
There are slightly different I/O characteristics for each module. I/Os for the MCU module are
designated as Ports 1, 3, and 4. I/Os for the PSD module are designated as Ports A, B, C,
and D.
) _{For all 5 V UPSD33xx devices, a 3.3 V MCU module is stacked with a 5 V PSD module. In}
t(s ^{this case, a 5 V UPSD33xx device must be supplied with 3.3 V}CC ^{for the MCU module and}
c _{5.0VDD for the PSD module. Ports 3 and 4 of the MCU module are 3.3 V ports with tolerance}
u _{to 5 V devices (they can be directly driven by external 5 V devices and they can directly}
rod ^{drive external 5 V devices while producing a VOH of 2.4 V min and VCC max). Ports A, B, C,}
and D of the PSD module are true 5 V ports.
P _{For all 3.3 V UPSD33xxV devices, a 3.3 V MCU module is stacked with a 3.3 V PSD}
te _{module. In this case, a 3.3 V UPSD33xx device needs to be supplied with a single 3.3 V}
le voltage source at both V_CC and V_DD. I/O pins on Ports 3 and 4 are 5 V tolerant and can be
o _{connected to external 5 V peripherals devices if desired. Ports A, B, C, and D of the PSD}
s _{module are 3.3 V ports, which are not tolerant to external 5 V devices.}
Ob _{Refer to Table 3 on page 27 for port type and voltage source requirements.}
) ^{- 80-pin UPSD33xx devices provide access to 8032 address, data, and control signals on}
t(s ^{external pins to connect external peripheral and memory devices. 52-pin UPSD33xx}
devices do not provide access to the 8032 system bus.
uc _{All non-volatile memory and configuration portions of the UPSD33xx device are}
d _{programmed through the JTAG interface and no special programming voltage is needed.}
ro _{This same JTAG port is also used for debugging of the 8032 core at runtime providing}
P _{breakpoint, single-step, display, and trace features. A non-volatile security bit may be}
te^{programmed to block all access via JTAG interface for security. The security bit is defeated}
Obsole^{only by erasing the entire device, leaving the device blank and ready to use again.}
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Doc ID 9685 Rev 7