UPSD3354DV-40U6 Datasheet, PDF (132/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

I²C interface
UPSD33xx
Table 79.
Bit
7:1
0
S1ADR register bit definition
Symbol
R/W
Function
SLA[6:0]
R/W
Stores desired 7-bit device address, used when SIOE is in
Slave mode.
–
–
Not used
23.12 I²C START sample setting (S1SETUP)
The S1SETUP register (Table 80 on page 132) determines how many times an I²C bus
START condition will be sampled before the SIOE validates the START condition, giving the
SIOE the ability to reject noise or illegal transmissions.
Because the minimum duration of an START condition varies with I²C bus speed (f_SCL), and
also because the UPSD33xx may be operated with a wide variety of frequencies (f_OSC), it is
necessary to scale the number of samples per START condition based on f_OSC and f_SCL.
Obsolete ^{Product(s) - Obsolete Product(s) Note:}
In Slave mode, the SIOE recognizes the beginning of a START condition when it detects a
1-to-0 transition on the SDA bus line while the SCL line is high (see Figure 38 on page 124).
The SIOE must then validate the START condition by sampling the bus lines to ensure SDA
remains low and SCL remains high for a minimum amount of hold time, t_HLDSTA. Once
validated, the SIOE begins receiving the address byte that follows the START condition.
If the EN_SS Bit (in the S1SETUP register) is not set, then the SIOE will sample only once
after detecting the 1-to-0 transition on SDA. This single sample is taken 1/f_OSC seconds
after the initial 1-to-0 transition was detected. However, more samples should be taken to
ensure there is a valid START condition.
To take more samples, the SIOE should be initialized such that the EN_SS Bit is set, and a
value is written to the SMPL_SET[6:0] field of the S1SETUP register to specify how many
samples to take. The goal is to take a good number of samples during the minimum START
condition hold time, t_HLDSTA, but no so many samples that the bus will be sampled after
t_HLDSTA expires.
Table 82 describes the relationship between the contents of S1SETUP and the resulting
number of I²C bus samples that SIOE will take after detecting the 1-to-0 transition on SDA of
a START condition.
Important: Keep in mind that the time between samples is always 1/f_OSC.
The minimum START condition hold time, t_HLDSTA, is different for the three common I²C
speed categories per Table 83 on page 133.
Table 80.
Bit 7
EN_SS
S1SETUP: I²C START Condition Sample Setup register (SFR DBh, reset
value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMPL_SET[6:0]
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Doc ID 9685 Rev 7