UPSD3354DV-40U6 Datasheet, PDF (262/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

DC and AC parameters
Figure 95. Peripheral I/O WRITE timing
ALE
UPSD33xx
A/D BUS
ADDRESS
DATA OUT
tWLQV (PA)
tWHQZ (PA)
WR
tDVQV (PA)
PORT A
DATA OUT
AI06611
Table 185. Port A peripheral data mode WRITE Timing (5 V PSD module)
t(s) ^Symbol
Parameter
Conditions
Min
Max Unit
c t_WLQV–PA WR to data propagation delay
du ^tDVQV–PA ^{Data to Port A data propagation delay}
(1)
ro t_WHQZ–PA WR Invalid to Port A Tri-state
P _{1. Data stable on Port 0 pins to data on Port A.}
25
ns
22
ns
20
ns
lete _{Table 186. Port A peripheral data mode WRITE Timing (3 V PSD module)}
so _Symbol
Parameter
Conditions
Min
Max Unit
Ob ^tWLQV–PA ^{WR to data propagation delay}
- _{tDVQV–PA Data to Port A data propagation delay}
(1)
t(s) ^{tWHQZ–PA WR Invalid to Port A Tri-state}
c 1. Data stable on Port 0 pins to data on Port A.
42
ns
38
ns
33
ns
rodu ^{Table 187. Supervisor Reset and LVD.}
P _Symbol
Parameter
Conditions
Min
Typ
Max Unit
te_{tRST_LO_IN Reset input duration}
1⁽¹⁾
µs
le_{tRST_ACTV Generated Reset duration}
f_OSC = 40 MHz
10⁽²⁾
ms
so _{tRST_FIL}
Reset input spike filter
1
µs
Ob ^VRST_HYS ^{Reset input hysteresis}
V_CC = 3.3 V
0.1
V
V_{RST_THRE LVD trip threshold}
SH
V_CC = 3.3 V
2.4
2.6
2.8
V
1. 25µs minimum to abort a Flash memory program or erase cycle in progress.
2. As F_OSC decreases, t_{RST_ACTV} increases. Example: t_{RST_ACTV} = 50ms when F_OSC = 8 MHz
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Doc ID 9685 Rev 7