UPSD3354DV-40U6 Datasheet, PDF (190/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
on the PSD module as an input to both PLDs (without routing a signal externally on PC
board) and it’s signal name is “rd_bsy”. The Ready/Busy output can be probed during lab
development to check the timing of Flash memory programming in the system at run-time.
27.4.13 Bypassed Unlock sequence
The Bypass Unlock mode allows the 8032 to program bytes in the Flash memories faster
than using the standard Flash program instruction sequences because the typical AAh, 55h
unlock bus cycles are bypassed for each byte that is programmed. Bypassing the unlock
sequence is typically used when the 8032 is intentionally programming a large number of
bytes (such as during IAP). After intentional programming is complete, typically the Bypass
mode would be disabled, and full protection is back in place to prevent unwanted WRITEs to
Flash memory.
The Bypass Unlock mode is entered by first initiating two Unlock bus cycles. This is followed
by a third WRITE operation containing the Bypass Unlock command, 20h (as shown in
Table 117 on page 184). The Flash memory array that received that sequence then enters
the Bypass Unlock mode. After this, a two bus cycle program operation is all that is required
to program a byte in this mode. The first bus cycle in this shortened program instruction
) sequence contains the Bypassed Unlocked Program command, A0h, to any valid address
t(s ^{within the unlocked Flash array. The second bus cycle contains the address and data of the}
byte to be programmed. Programming status is checked using toggle, polling, or
uc Ready/Busy just as before. Additional data bytes are programmed the same way until this
d _{Bypass Unlock mode is exited.}
ro _{To exit Bypass Unlock mode, the system must issue the Reset Bypass Unlock instruction}
P _{sequence. The first bus cycle of this instruction must write 90h to any valid address within}
te ^{the unlocked Flash Array; the second bus cycle must write 00h to any valid address within}
le ^{the unlocked Flash Array. After this sequence the Flash returns to Read Array mode.}
o _{During Bypass Unlock mode, only the Bypassed Unlock Program instruction, or the Reset}
bs ^{Bypass Unlock instruction is valid, other instruction will be ignored.}
t(s) ^{- O 27.4.14}
Erasing Flash memory
Flash memory may be erased sector-by-sector, or an entire Flash memory array may be
erased with one command (bulk).
Obsolete ^{Produc 27.4.15}
Flash bulk Erase
The Flash Bulk Erase instruction sequence uses six WRITE operations followed by a READ
operation of the status register, as described in Table 117 on page 184. If any byte of the
Bulk Erase instruction sequence is wrong, the Bulk Erase instruction sequence aborts and
the device is reset to the Read Array mode. The address provided by the 8032 during the
Flash Bulk Erase command sequence may select any one of the eight Flash memory sector
select signals FSx or one of the four signals CSBOOTx. An erase of the entire Flash
memory array will occur in a particular array even though a command was sent to just one of
the individual Flash memory sectors within that array.
During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit
(DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7). The Error Flag Bit
(DQ5) returns a ’1’ if there has been an erase failure. Details of acquiring the status of the
Bulk Erase operation are detailed in Section 27.4.9: Programming Flash memory on
page 186.
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