UPSD3354DV-40U6 Datasheet, PDF (51/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
UPSD33xx instruction set summary
Table 6.
Arithmetic instruction set (continued)
Mnemonic⁽¹⁾
and use
Description
Length/cycles
INC
INC
INC
DEC
Rn
direct
@Ri
A
Increment register
Increment direct byte
Increment indirect SRAM
Decrement ACC
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
DEC
DEC
DEC
INC
MUL
Rn
direct
@Ri
DPTR
AB
Decrement register
Decrement direct byte
Decrement indirect SRAM
Increment Data Pointer
Multiply ACC and B
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
1 byte/2 cycle
1 byte/4 cycle
DIV
AB
Divide ACC by B
) DA
A
Decimal adjust ACC
t(s ^{1. All mnemonics copyrighted ©Intel Corporation 1980.}
Produc ^{Table 7.}
Logical instruction set
Mnemonic⁽¹⁾
and use
Description
te _ANL
A, Rn
AND register to ACC
ole ANL
A, direct
AND direct byte to ACC
bs ^ANL
A, @Ri
AND indirect SRAM to ACC
O _ANL
) ^{- ANL}
t(s ANL
uc _ORL
rod ^ORL
P _ORL
A, #data
direct, A
direct, #data
A, Rn
A, direct
A, @Ri
AND immediate data to ACC
AND ACC to direct byte
AND immediate data to direct
byte
OR register to ACC
OR direct byte to ACC
OR indirect SRAM to ACC
teORL
le_ORL
Obso ^ORL
A, #data
direct, A
direct, #data
OR immediate data to ACC
OR ACC to direct byte
OR immediate data to direct
byte
1 byte/4 cycle
1 byte/1 cycle
Length/cycles
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
2 byte/1 cycle
3 byte/2 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
2 byte/1 cycle
3 byte/2 cycle
SWAP
A
Swap nibbles within the ACC
1 byte/1 cycle
XRL
A, Rn
Exclusive-OR register to ACC
1 byte/1 cycle
XRL
A, direct
Exclusive-OR direct byte to
ACC
2 byte/1 cycle
Doc ID 9685 Rev 7
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