UPSD3354DV-40U6 Datasheet, PDF (143/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Synchronous peripheral interface (SPI)
configuration (which means the user does not have to use the SPISEL signal from
UPSD33xx in this case).
The SPI specification does not specify high-level protocol for data exchange, only low-level
bit-serial transfers are defined.
24.2
Full-duplex operation
When an SPI transfer occurs, 8 bits of data are shifted out on one pin while a different 8 bits
of data are simultaneously shifted in on a second pin. Another way to view this transfer is
that an 8-bit shift register in the Master and another 8-bit shift register in the Slave are
connected as a circular 16-bit shift register. When a transfer occurs, this distributed shift
register is shifted 8 bit positions; thus, the data in the Master and Slave devices are
effectively exchanged (see Figure 41 on page 143).
24.3 Bus-level activity
Product(s) ^Note:
Figure 42 on page 144 details an SPI receive operation (with respect to bus Master) and
Figure 43 on page 144 details an SPI transmit operation. Also shown are internal flags
available to firmware to manage data flow. These flags are accessed through a number of
SFRs.
The UPSD33xx SPI interface SFRs allow the choice of transmitting the most significant bit
(MSB) of a byte first, or the least significant bit (LSB) first. The same bit-order applies to data
reception. Figure 42 and Figure 43 illustrate shifting the LSB first.
lete ^{Figure 41. SPI full-duplex data exchange}
o Master Device
bs _{8-Bit Shift}
- ^{O Register}
SPIRxD
SPITxD
SPI Bus
Slave Device
MISO
MOSI
8-Bit Shift
Register
t(s) ^SPICLK
SCLK
duc _{Baud Rate}
Obsolete ^{Pro Generator}
SS
AI10485
Doc ID 9685 Rev 7
143/272