UPSD3354DV-40U6 Datasheet, PDF (88/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

MCU bus interface
UPSD33xx
Table 49. Number of MCU_CLK periods required to optimize bus transfer rate
MCU clock frequency,
MCU_CLK (f_MCU)
CW[1:0] Clk
periods
3.3 V⁽¹⁾ 5 V⁽¹⁾
RDW[1:0] Clk
periods
3.3 V⁽¹⁾ 5 V⁽¹⁾
WRW[1:0] Clk
periods
3.3 V⁽¹⁾ 5 V⁽¹⁾
40 MHz, Turbo mode PSD⁽²⁾
5
4
5
4
5
4
40 MHz, Non-Turbo mode PSD
6
5
6
5
6
5
36 MHz, Turbo mode PSD
5
4
5
4
5
4
36 MHz, Non-Turbo mode PSD
6
4
6
4
6
4
32 MHz, Turbo mode PSD
5
4
5
4
5
4
32 MHz, Non-Turbo mode PSD
5
4
5
4
5
4
28 MHz, Turbo mode PSD
4
3
4
4
4
4
28 MHz, Non-Turbo mode PSD
5
4
5
4
5
4
24 MHz, Turbo mode PSD
4
3
4
4
4
4
) 24 MHz, Non-Turbo mode PSD
4
3
4
4
4
4
t(s ^{20 MHz and below, Turbo mode PSD 3}
3
4
4
4
4
c _{20 MHz and below, Non-Turbo mode}
du ^PSD
3
3
4
4
4
4
ro 1. V_DD of the PSD module
P _{2. “Turbo mode PSD” means that the PSD module is in the faster, Turbo mode (default condition). A PSD}
module in Non-Turbo mode is slower, but consumes less current. See PSD module section, titled “PLD
Obsolete ^{Product(s) - Obsolete Non-Turbo mode” for details.}
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Doc ID 9685 Rev 7