UPSD3354DV-40U6 Datasheet, PDF (89/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
19 Supervisory functions
Supervisory functions
Supervisory circuitry on the MCU module will issue an internal reset signal to the MCU
module and simultaneously to the PSD module as a result of any of the following four
events:
● The external RESET_IN pin is asserted
● The low voltage Detect (LVD) circuitry has detected a voltage on V_CC below a specific
threshold (power-on or voltage sags)
● The JTAG debug interface has issued a reset command
● The Watch Dog Timer (WDT) has timed out
The resulting internal reset signal, MCU_RESET, will force the 8032 into a known reset state
while asserted, and then 8032 program execution will jump to the reset vector at program
address 0000h just after MCU_RESET is deasserted. The MCU module will also assert an
active low internal reset signal, RESET, to the PSD module. If needed, the signal RESET
can be driven out to external system components through any PLD output pin on the PSD
module. When driving this “RESET_OUT” signal from a PLD output, the user can choose to
) _{make it either active-high or active-low logic, depending on the PLD equation.}
t(s) ^{- Obsolete Product(s 19.1}
External reset input pin, RESET_IN
The RESET_IN pin can be connected directly to a mechanical reset switch or other device
which pulls the signal to ground to invoke a reset.
RESET_IN is pulled up internally and enters a Schmitt trigger input buffer with a voltage
hysteresis of V_{RST_HYS} for immunity to the effects of slow signal rise and fall times, as
shown in Figure 19. RESET_IN is also filtered to reject a voltage spike less than a duration
of t_{RST_FIL}. The RESET_IN signal must be maintained at a logic '0' for at least a duration of
t_{RST_LO_IN} while the oscillator is running. The resulting MCU_RESET signal will last only as
long as the RESET_IN signal is active (it is not stretched). Refer to the Supervisor AC
specifications in Table 187 on page 262 at the end of this document for these parameter
values.
c _{Figure 19. Supervisor Reset generation}
duVCC
lete ^Pro _{RESET_IN}
o _PIN
Obs ^WDT
PULL-UP
Noise Filter
MCU
Clock
Sync
MCU_RESET
to MCU and
Peripherals
LVD
JTAG Debug
S
Q
DELAY,
tRST_ACTV
R
RESET
to PSD Module
AI09603
Doc ID 9685 Rev 7
89/272