UPSD3354DV-40U6 Datasheet, PDF (124/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

I²C interface
UPSD33xx
A few things to know related to these transfers:
● Either the Master or Slave device can hold the SCL clock line low to indicate it needs
more time to handle a byte transfer. An indefinite holding period is possible.
● A START condition is generated by a Master and recognized by a Slave when SDA has
a 1-to-0 transition while SCL is high (Figure 38).
● A STOP condition is generated by a Master and recognized by a Slave when SDA has
a 0-to1 transition while SCL is high (Figure 38).
● A RE-START (repeated START) condition generated by a Master can have the same
function as a STOP condition when starting another data transfer immediately following
the previous data transfer (Figure 38).
● When transferring data, the logic level on the SDA line must remain stable while SCL is
high, and SDA can change only while SCL is low. However, when not transferring data,
SDA may change state while SCL is high, which creates the START and STOP bus
conditions.
● An Acknowledge bit is generated from a Master or a Slave by driving SDA low during
the “ninth” bit time, just following each 8-bit byte that is transferred on the bus
(Figure 38). A Non-Acknowledge occurs when SDA is asserted high during the ninth bit
) _{time. All byte transfers on the I}²_{C bus include a 9th bit time reserved for an}
t(s ^{Acknowledge (ACK) or Non-Acknowledge (NACK).}
c ● An additional Master device that desires to control the bus should wait until the bus is
u _{not busy before generating a START condition so that a possible Slave operation is not}
d _interrupted.
ro _{● If two Master devices both try to generate a START condition simultaneously, the}
P _{Master who looses arbitration will switch immediately to Slave mode so it can recognize}
te ^{it’s own Slave address should it appear on the bus.}
ole Figure 38. Data transfer on an I²C bus
Obs 7-bit Slave
- ^Address
READ/WRITE
Indicator
uct(s) ^MSB
R/W ACK
Acknowledge
bits from
receiver
MSB
NACK
ACK
Stop
Condition
Repeated
Start
Condition
te ^{Prod Start}
Obsole ^Condition
1
2
3-6
7
8
9
Clock can be held low
to stall transfer.
1
2
3-8
9
Repeated if more
data bytes are
transferred.
AI09625
124/272
Doc ID 9685 Rev 7