UPSD3354DV-40U6 Datasheet, PDF (255/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
DC and AC parameters
Figure 89. Input to output disable / enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Table 174. CPLD combinatorial timing (5 V PSD module)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate⁽¹⁾
Unit
t_PD(2)
CPLD input pin/feedback to CPLD
combinatorial output
20 + 2 + 10
–2
ns
t_EA
CPLD input to CPLD Output
Enable
21
+ 10
–2
ns
t(s) ^tER
CPLD Input to CPLD Output
Disable
21
+ 10
–2
ns
duc ^tARP
CPLD register Clear or Preset
delay
21
+ 10
–2
ns
Pro ^tARPW
CPLD register Clear or Preset
pulse width
10
+ 10
ns
te ^tARD ^{CPLD array delay}
Any macrocell
11 + 2
ns
le _{1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount}
so 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD
combinatorial output (80-pin package only)
- ^Ob _{Table 175. CPLD combinatorial timing (3 V PSD module)}
ct(s) ^Symbol
Parameter
Conditions Min Max
PT
Aloc
Turbo
Off
Slew
rate
(1)
Unit
rodu ^tPD(2)
P _tEA
te _tER
ole ^tARP
Obs^tARPW
CPLD input pin/feedback to CPLD
combinatorial output
CPLD input to CPLD Output Enable
CPLD input to CPLD Output Disable
CPLD register Clear or Preset delay
CPLD register Clear or Preset pulse
width
35
+4
+ 15 – 6 ns
38
+15 – 6 ns
38
+ 15 – 6 ns
35
+ 15 – 6 ns
18
+ 15
ns
t_ARD CPLD Array Delay
Any
macrocell
20
+4
ns
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t_PD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD
combinatorial output (80-pin package only)
Doc ID 9685 Rev 7
255/272