UPSD3354DV-40U6 Datasheet, PDF (44/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Special function registers (SFR)
UPSD33xx
Table 5. SFR memory map with direct address and reset value (continued)
SFR
addr
SFR
(hex)
name
7
6
Bit name and <Bit Address>
5
4
3
2
1
0
Reset
value
(hex)
Reg. descr.
with link
D4
SPITDR
D5 SPIRDR
SPITDR[7:0]
SPIRDR[7:0]
00
Table 91 on
00
page 149
D6 SPICON0
–
TE
RE
SPIEN
SSEL
FLSB
SPO
–
00
Table 85 on
page 147
D7 SPICON1
–
–
–
–
TEIE
RORIE
TIE
RIE
00
Table 87 on
page 148
D8⁽¹⁾ SCON1
SM0
<DF
SM1
<DE>
SM2
<DD>
REN
<DC>
TB8
<DB>
RB8
<DA>
TI
<D9>
RI
<D8>
00
Table 65 on
page 109
D9
SBUF1
SBUF1[7:0]
00
Figure 24 on
page 104
DA
RESERVED
DB S1SETUP SS_EN
SMPL_SET[6:0]
00
Table 80 on
page 132
DC
S1CON
t(s) DD
S1STA
uc _DE
S1DAT
rod _DF
S1ADR
te ^{P E0(1)}
A
le _E1
o _to
s _EF
Ob ^F0(1)
B
- _F1
t(s) ^F2
c ^F3
u _F4
rod ^F5
F6
te ^{P F7}
le ^F8
o _F9
CCON0
Obs^FA
CR2
GC
–
EN1
STA
STO
ADDR
AA
CR1
CR0
00
Table 71 on
page 128
STOP
INTR
TX_MD B_BUSY B_LOST ACK_R SLV
00
Table 74 on
page 130
S1DAT[7:0]
00
Table 76 on
page 131
S1ADR[7:0]
00
Table 78 on
page 131
A[7:0]
<bit addresses: E7h, E6h, E5h, E4h, E3h, E2h, E1h, E0h>
00
Section 7.4
on page 38
RESERVED
B[7:0]
<bit addresses: F7h, F6h, F5h, F4h, F3h, F2h, F1h, F0h>
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
–
–
DBGCE CPU_AR
CPUPS[2:0]
RESERVED
00
Section 7.5
on page 38
10
Table 27 on
page 69
FB
CCON2
–
–
–
PCA0CE
PCA0PS[3:0]
10
Table 99 on
page 154
FC
CCON3
–
–
–
PCA1CE
PCA1PS[3:0]
10
Table 101 on
page 155
FD
RESERVED
44/272
Doc ID 9685 Rev 7