UPSD3354DV-40U6 Datasheet, PDF (194/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
Note:
The AND-OR array is used to form product terms. These product terms are configured from
the logic definitions entered in PSDsoft Express. A PLD Input Bus consisting of 69 signals is
connected to both PLDs. Input signals are shown in Table 121 on page 194, both the true
and compliment versions of each of these signals are available at inputs to each PLD.
The 8032 data bus, D0 - D7, does not route directly to PLD inputs. Instead, the 8032 data
bus has indirect access to the GPLD (not the DPLD) when the 8032 reads and writes the
OMC and IMC registers within csiop address space.
27.4.25 Turbo Bit and PLDs
The PLDs can minimize power consumption by going to standby after ALL the PLD inputs
remain unchanged for an extended time (about 70ns). When the Turbo Bit is set to logic one
(Bit 3 of the csiop PMMR0 register), Turbo mode is turned off and then this automatic
standby mode is achieved. Turning off Turbo mode increases propagation delays while
reducing power consumption. The default state of the Turbo Bit is logic zero, meaning Turbo
mode is on. Additionally, four bits are available in the csiop PMMR0 and PMMR2 registers to
block the 8032 bus control signals (RD, WR, PSEN, ALE) from entering the PLDs. This
reduces power consumption and can be used only when these 8032 control signals are not
) used in PLD logic equations. See Section 27.4.51: Power management on page 224.
t(s _{Table 121. DPLD and GPLD inputs}
duc Input source
ro _{8032 address bus}
te ^{P 8032 bus control signals}
le ^{Reset from MCU module}
o _{Power-down from Auto-Power-down counter}
bs _{PortA Input macrocells}
O _{(80-pin devices only)}
) ^- PortB input macrocells
t(s ^{PortC input macrocells}
c _{Port D inputs}
du (52-pin devices have only PD1)
ro _{Page register}
te ^{P Macrocell OMC bank AB feedback}
ole_{Macrocell OMC bank BC feedback}
Obs ^{Flash Memory Status bit}
Input name
A0-A15
PSEN, RD, WR, ALE
RESET
PDN
PA0-PA7
PB0-PB7
PC2, PC3, PC4, PC7
PD1, PD2
PGR0-PGR7
MCELLAB
FB0-7
MCELLBC
FB0-7
Ready/Busy
Number of
signals
16
4
1
1
8
8
4
2
8
8
8
1
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Doc ID 9685 Rev 7