UPSD3354DV-40U6 Datasheet, PDF (50/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx instruction set summary
10 UPSD33xx instruction set summary
UPSD33xx
Table 6, Table 7, Table 8, Table 9, Table 10, and Table 11 list all of the instructions supported
by the UPSD33xx, including the number of bytes and number of machine cycles required to
implement each instruction. This is the standard 8051 instruction set.
The meaning of “machine cycles” is how many 8032 MCU core machine cycles are required
to execute the instruction. The “native” duration of all machine cycles is set by the memory
wait state settings in the SFR, BUSCON, and the MCU clock divider selections in the SFR,
CCON0 (i.e. a machine cycle is typically set to 4 MCU clocks for a 5 V UPSD33xx).
However, an individual machine cycle may grow in duration when either of two things
happen:
1. Astall is imposed while loading the 8032 Pre-Fetch Queue (PFQ); or
2. The occurrence of a cache miss in the Branch Cache (BC) during a branch in program
execution flow.
See Section 5: 8032 MCU core performance enhancements on page 32 or more details.
) But generally speaking, during typical program execution, the PFQ is not empty and the BC
t(s ^{has no misses, producing very good performance without extending the duration of any}
machine cycles.
uc _{The UPSD33xx programmers guide describes each instruction operation in detail.}
te ^{Prod Table 6.}
Arithmetic instruction set
Mnemonic⁽¹⁾
and use
Description
ole ADD
bs ^ADD
A, Rn
A, Direct
Add register to ACC
Add direct byte to ACC
O _ADD
) ^{- ADD}
t(s ^ADDC
uc ADDC
rod _ADDC
te ^P ADDC
A, @Ri
A, #data
A, Rn
A, direct
A, @Ri
A, #data
Add indirect SRAM to ACC
Add immediate data to ACC
Add register to ACC with carry
Add direct byte to ACC with
carry
Add indirect SRAM to ACC
with carry
Add immediate data to ACC
with carry
ole_SUBB
Obs _SUBB
A, Rn
A, direct
Subtract register from ACC
with borrow
Subtract direct byte from ACC
with borrow
Length/cycles
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
SUBB
A, @Ri
Subtract indirect SRAM from
ACC with borrow
1 byte/1 cycle
SUBB
A, #data
Subtract immediate data from
ACC with borrow
2 byte/1 cycle
INC
A
Increment A
1 byte/1 cycle
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Doc ID 9685 Rev 7