UPSD3354DV-40U6 Datasheet, PDF (223/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
Port D pins can also be configured in PSDsoft as pins for other dedicated functions:
● PD1 can be used as a common clock input to all 16 OMC Flip-flops (see
Section 27.1.11: OMCs on page 168) and also Section 27.4.52: Automatic Power-down
(APD) on page 227.
● PD2 can be used as a common chip select signal (CSI) for the Flash and SRAM
memories on the PSD module (see Section 27.4.54: Chip Select Input (CSI) on
page 230). If driven to logic ’1’ by an external source, CSI will force all memories into
standby mode regardless of what other internal memory select signals are doing on the
PSD module. This is specified in PSDsoft as “PSD Chip Select Input, CSI”.
Port D also supports the Fast Slew Rate output drive type option using the csiop Drive
Select registers.
Figure 76. Port D structure
FROM AND-
OR ARRAY
PT OUTPUT ENABLE (.OE)
I/O PORT D
LOGIC
FROM PLD
bsolete ^{Product(s) INPUTBUS}
PSD MODULE RESET
Q ^DIRECTION
CSIOP
REGIS-
8032
DATA
TERS
Q
DRIVE
BITS _D
8032
WR
(MCUI/O)
Q ^{DATA OUT}
CLR
RESET
t(s) ^{- O} ₈₀₃₂
c _DATA
Produ ^BIT
P ^{1 DIRECTION}
D ₂ ^{DRIVE SELECT}
B DATA OUT
M
U
3
4
(MCUI/O)
ENABLE OUT
X ₅ DATA IN (MCUI/O)
olete^{8032 RD}
ONE of 5
CSIOP
REGISTERS
PSDsoft
1^O
U
T
P
U
2T
M
U
X
Obs ^{FROM DPLD}
FROM DPLD EXTERNAL CHIP (ECSx)
DRIVE TYPE SELECT
1 = FAST
SLEW RATE
OUTPUT
ENABLE
PIN
OUTPUT
OUTPUT
ENABLE
V_DD V_DD
TYPICAL
PIN, PORT D
CMOS
BUFFER _{PIN INPUT}
NO
HYSTERESIS
TO POWER MANAGEMENT AND PLD INPUT BUS
TO POWER MANAGEMENT
DIRECTLY TO PLD INPUT BUS, NO IMC
CLKIN⁽¹⁾
CSI⁽¹⁾
PD1. PIN, PD2.PIN
AI09182
1. Optional function on a specific Port D pin.
Doc ID 9685 Rev 7
223/272