UPSD3354DV-40U6 Datasheet, PDF (116/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Serial UART interfaces
UPSD33xx
21.6 More about UART modes 2 and 3
For mode 2, refer to the block diagram in Figure 31 on page 117, and timing diagram in
Figure 32 on page 117. For mode 3, refer to the block diagram in Figure 33 on page 118,
and timing diagram in Figure 34 on page 118.
Keep in mind that the baud rate is programmable to either 1/32 or 1/64 of f_OSC in mode 2,
but mode 3 uses a variable baud rate generated from Timer 1 or Timer 2 rollovers.
The receive portion is exactly the same as in mode 1. The transmit portion differs from mode
1 only in the 9th bit of the transmit shift register.
Transmission is initiated by any instruction which writes to SBUF. At the end of a write
operation to SBUF, the TB8 Bit is loaded into the 9th position of the transmit shift register
and flags the TX Control unit that a transmission is requested. Transmission actually starts
at the end of the MCU the machine cycle following the next rollover in the divide-by-16
counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the writing
of SBUF. Transmission begins with activation of SEND which puts the start bit at pin TxD.
One bit time later, DATA is activated, which enables the output bit of the transmit shift
register to pin TxD. The first shift pulse occurs one bit time after that. The first shift clocks a
) '1' (the stop bit) into the 9th bit position of the shift register. There-after, only zeros are
t(s ^{clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When}
bit TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8,
uc and all positions to the left of that contain zeros. This condition flags the TX Control unit to
d _{do one last shift and then deactivate SEND, and set the interrupt flag, TI. This occurs at the}
ro ^{11th divide-by 16 rollover after writing to SBUF.}
P _{Reception is initiated by a detected 1-to-0 transition at pin RxD. For this purpose RxD is}
te ^{sampled at a rate of 16 times whatever baud rate has been established. When a transition is}
le ^{detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift}
o ^{register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the}
s _{value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If}
b _{the value accepted during the first bit time is not '0,' the receive circuits are reset and the}
O _{unit goes back to looking for another '1'-to-'0' transition. If the start bit proves valid, it is}
- _{shifted into the input shift register, and reception of the rest of the frame will proceed. As}
) _{data bits come in from the right, '1s' shift out to the left. When the start bit arrives at the left-}
t(s ^{most position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the RX}
c _{Control unit to do one last shift, load SBUF and RB8, and set the interrupt flag RI. The signal}
u _{to load SBUF and RB8, and to set RI, will be generated if, and only if, the following}
d _{conditions are met at the time the final shift pulse is generated:}
ro _{● RI = 0, and}
P _{● Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met,}
te_{the received frame is irretrievably lost, and RI is not set. If both conditions are met, the}
le received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time
o _{later, whether the above conditions were met or not, the unit goes back to looking for a}
Obs ^{'1'-to-'0' transition on pin RxD.}
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Doc ID 9685 Rev 7