UPSD3354DV-40U6 Datasheet, PDF (196/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
27.4.26 Decode PLD (DPLD)
The DPLD (Figure 63 on page 197) generates the following memory decode signals:
● Eight main Flash memory sector select signals (FS0-FS7) with three product terms
each
● Four secondary Flash memory sector select signals (CSBOOT0-CSBOOT3) with three
product terms each
● One SRAM select signal (RS0) with two product terms
● One select signal for the base address of 256 PSD module device control and status
registers (CSIOP) with one product term
● Two external chip-select output signals for Port D pins, each with one product term (52-
pin devices only have one pin on Port D)
● Two chip-select signals (PSEL0, PSEL1) used to enable the 8032 data bus repeater
function (Peripheral I/O mode) for Port A on 80-pin devices. Each has one product
term.
A product term indicates the logical OR of two or more inputs. For example, three product
terms in a DPLD output means the final output signal is capable of representing the logical
) _{OR of three different input signals, each input signal representing the logical AND of a}
t(s ^{combination of the 69 PLD inputs.}
c _{Using the signal FS0 for example, the user may create a 3-product term chip select signal}
du that is logic true when any one of three different address ranges are true... FS0 = address
ro ^{range 1 OR address range 2 OR address range 3.}
P _{The phrase “one product term” is a bit misleading, but commonly used in this context. One}
te ^{product term is the logical AND of two or more inputs, with no OR logic involved at all, such}
Obsolete ^{Product(s) - Obsole as the CSIOP signal in Figure 63 on page 197.}
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Doc ID 9685 Rev 7