UPSD3354DV-40U6 Datasheet, PDF (241/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
The Debug signal should always be pulled up externally with a weak pull-up (100K
minimum) to V_CC even if nothing is connected to it, as shown in Figure 80 and Figure 81 on
page 238.
27.5.9 JTAG security setting
A programmable security bit in the PSD module protects its contents from unauthorized
viewing and copying. The security bit is set by clicking on the “Additional PSD Settings” box
in the main flow diagram of PSDsoft Express, then choosing to set the security bit. Once a
file with this setting is programmed into a UPSD33xx using JTAG ISP, any further attempts
to communicate with the UPSD33xx using JTAG will be limited. Once secured, the only
JTAG operation allowed is a full-chip erase. No reading or modifying Flash memory or PLD
logic is allowed. debugging operations to the MCU module are also not allowed. The only
way to defeat the security bit is to perform a JTAG ISP full-chip erase operation, after which
the device is blank and may be used again. The 8032 on the MCU module will always have
access to PSM module memory contents through the 8-bit 8032 data bus connecting the
two die, even while the security bit is set.
Obsolete ^{Product(s) - Obsolete Product(s) 27.5.10}
Initial delivery state
When delivered from STMicroelectronics, UPSD33xx devices are erased, meaning all Flash
memory and PLD configuration bits are logic '1.' Firmware and PLD logic configuration must
be programmed at least the first time using JTAG ISP. Subsequent programming of Flash
memory may be performed using JTAG ISP, JTAG debugging, or the 8032 may run firmware
to program Flash memory (IAP).
Doc ID 9685 Rev 7
241/272