UPSD3354DV-40U6 Datasheet, PDF (220/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
Figure 74. Port B structure
FROM AND-
OR ARRAY
PT OUTPUT ENABLE (.OE)
I/O PORT B
LOGIC
FROM PLD
PSD MODULE RESET
INPUT BUS
Q ^DIRECTION
CSIOP
REGIS-
8032 ^TERS
DATA
Q
DRIVE
DRIVE TYPE SELECT⁽¹⁾
BITS _D
PSDsoft
1 = OPEN
DRAIN,
1 = FAST
SLEW RATE,
8032
WR
Q ^CONTROL
OUTPUT
SELECT
PB4 - PB7
PB0 - PB3
V_DD V_DD
(MCUI/O)
Q ^{DATA OUT}
1^O
OUTPUT
U
ENABLE
T
TYPICAL
Obsolete ^Product(s) _FROMOMC
t(s) ^{- ALLOCATOR}
CLR
RESET
LATCHED ADDR BIT
8032
DATA
BIT
1 ^DIRECTION
P ₂ ^{DRIVE SELECT}
D
B
3
CONTROL
DATA OUT
M ₄ ^(MCUI/O)
U ₅ ^{ENABLE OUT}
X ₆ DATA IN (MCUI/O)
8032 RD
ONE of 6
CSIOP
REGISTERS
FROM OMC OUTPUT
(MCELLABx or MCELLBCx)
P
PIN
U
OUTPUT
2T
OUTPUT
3_M
ENABLE
U
X
PIN, PORT B
CMOS
BUFFER _{PIN INPUT}
NO
HYSTERESIS
TO IMCs
IMCB0 - IMCB7
AI09180
uc 1. Port pins PB0-PB3 are capable of Fast Slew Rate output drive option. Port pins PB4-PB7 are capable of Open Drain output
d ^option.
Obsolete ^{Pro 27.4.49}
Port C structure
Port C supports the following operating modes on pins PC2, PC3, PC4, PC7:
● MCU I/O mode
● GPLD Output mode from Output Macrocells MCELLBC2, MCELLBC3, MCELLBC4,
MCELLBC7
● GPLD Input mode to Input Macrocells IMCC2, IMCC3, IMCC4, IMCC7
See Figure 75 on page 222 for detail.
Port C pins can also be configured in PSDsoft for other dedicated functions:
● Pins PC3 and PC4 support TSTAT and TERR status indicators, to reduce the amount
of time required for JTAG ISP programming. These two pins must be used together for
this function, adding to the four standard JTAG signals. When TSTAT and TERR are
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Doc ID 9685 Rev 7