UPSD3354DV-40U6 Datasheet, PDF (69/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
MCU clock generation
Figure 13. Clock generation logic
PCON[1]: PD,
Power-Down Mode
CCON[2:0]
Clock Pre-Scaler Select
PCON[0]: IDL,
Idle Mode
XTAL1
(fOSC)
XTAL1 (default)
3
0
Q ^{XTAL1 /2}
Q ^{XTAL1 /4}
Q ^{XTAL1 /8}
Q ^{XTAL1 /16}
Q ^{XTAL1 /32}
Q ^{XTAL1 /1024}
Q ^{XTAL1 /2048}
1
2_M
3_U
4X
5
6
7
MCU_CLK (fMCU)
(to: 8032, WDT)
Clock Divider
t(s) ^AI09197b
PERIPH_CLK (fOSC)
(to: TIMER0/1/2, UART0/1, PCA0/1, SPI, I2C, ADC)
uc _{Table 27.}
rod ^{Bit 7}
P _–
CCON0: Clock Control register (SFR F9h, reset value 10h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
DBGCE CPUAR
CPUPS[2:0]
Bit 0
lete Table 28. CCON0 register bit definition
so ^{Bit Symbol R/W}
Definition
b ₇
–
– Reserved
- ^O 6
–
– Reserved
t(s) ⁵
–
– Reserved
Debug Unit Breakpoint Comparator Enable
uc 4 DBGCE R,W 0 = JTAG debug unit comparators are disabled
d _{1 = JTAG debug unit comparators are enabled (Default condition after reset)}
ro _{Automatic MCU Clock Recovery}
P _{3 CPUAR R,W 0 = There is no change of CPUPS[2:0] when an interrupt occurs.}
te 1 = Contents of CPUPS[2:0] automatically become 000b whenever any
le ^{interrupt occurs.}
o _{MCUCLK Pre-Scaler}
bs 000b: f_MCU = f_OSC (Default after reset)
O 001b: f_MCU = f_OSC/2
010b: f_MCU = f_OSC/4
2:0 CPUPS R,W 011b: f_MCU = f_OSC/8
100b: f_MCU = f_OSC/16
101b: f_MCU = f_OSC/32
110b: f_MCU = f_OSC/1024
111b: f_MCU = f_OSC/2048
Doc ID 9685 Rev 7
69/272