UPSD3354DV-40U6 Datasheet, PDF (41/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Special function registers (SFR)
Table 5. SFR memory map with direct address and reset value
SFR
addr
SFR
(hex)
name
7
6
Bit name and <Bit Address>
5
4
3
2
1
0
Reset
value
(hex)
Reg. descr.
with link
80
RESERVED
81
SP
SP[7:0]
07
Section 7.1
on page 37
82
DPL
83
DPH
DPL[7:0]
DPH[7:0]
00
Section 7.2
00
on page 37
84
RESERVED
85
DPTC
–
AT
–
–
–
DPSEL[2:0]
00
Table 13 on
page 56
86
DPTM
–
–
–
–
MD1[1:0]
MD0[1:0]
00
Table 15 on
page 57
87
PCON
SMOD0 SMOD1
–
POR
RCLK1 TCLK1
PD
IDLE
00
Table 31 on
page 72
88⁽¹⁾
TCON
t(s) ⁸⁹
TMOD
c _8A
TL0
du 8B
TL1
ro 8C
TH0
P _8D
TH1
te _8E
P1SFS0
ole _8F
P1SFS1
bs ₉₀₍₁₎
P1
- ^O ₉₁
P3SFS
t(s) ₉₂
P4SFS0
uc ₉₃
P4SFS1
rod ₉₄
ADCPS
te ^{P 95}
ADAT0
le ₉₆
ADAT1
Obso ⁹⁷
ACON
TF1
<8Fh>
GATE
P1.7
<97h>
–
–
AINTF
TR1
<8Eh>
C/T
P1.6
<96h>
–
–
AINTEN
TF0
<8Dh>
M1
P1.5
<95h>
–
–
ADEN
TR0
<8Ch>
IE1
<8Bh>
IT1
<8Ah>
IE0
<89h>
IT0
<88h>
00
Table 54 on
page 95
M0
GATE
C/T
M1
M0
00
Table 56 on
page 97
TL0[7:0]
00
TL1[7:0]
TH0[7:0]
00
Section 20.1
00
on page 94
TH1[7:0]
00
P1SFS0[7:0]
00
Table 41 on
page 83
P1SFS1[7:0]
00
Table 42 on
page 83
P1.4
<94h>
P1.3
<93h>
P1.2
<92h>
P1.1
<91h>
P1.0
<90h>
FF
Table 33 on
page 80
P3SFS[7:0]
00
Table 39 on
page 83
P4SFS0[7:0]
00
Table 44 on
page 84
P4SFS1[7:0]
00
Table 45 on
page 84
–
ADCCE
ADCPS[2:0]
00
Table 95 on
page 152
ADATA[7:0]
00
Table 96 on
page 152
–
–
–
ADATA[9:8]
00
Table 97 on
page 152
ADS[2:0]
ADST ADSF
00
Table 93 on
page 151
98⁽¹⁾
SCON0
SM0
<9Fh>
SM1
<9Eh>
SM2
<9Dh>
REN
<9Ch>
TB8
<9Bh>
RB8
<9Ah>
TI
<99h>
RI
<9h8>
00
Table 63 on
page 108
99
SBUF0
SBUF0[7:0]
00
Figure 24 on
page 104
9A
RESERVED
9B
RESERVED
Doc ID 9685 Rev 7
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