UPSD3354DV-40U6 Datasheet, PDF (142/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Synchronous peripheral interface (SPI)
UPSD33xx
Figure 40. SPI device connection examples
UPSD33xx
SPI Master
SPIRxD
SPITxD
SPICLK
SPISEL
SPI Bus
MISO
MOSI
SCLK
SS
SPI Slave
Device
UPSD33xx
SPI Master
SPIRxD
SPITxD
SPICLK
SPI Bus
MISO
MOSI
SCLK
SS
SPI Slave
Device
Single-Master/Single-Slave, with SPISEL
Single-Master/Single-Slave, without SPISEL
SPI Bus
SPIRxD
MISO
SPITxD
SPICLK
MOSI
SCLK
SPI Slave
Device
GPIO or PLD
SS
UPSD33xx
SPI Mastecc
ct(s) _{GPIO or PLD}
MISO
MOSI
SCLK
SS
SPI Slave
Device
rodu ^{Single-Master/Multiple-Slave, without SPISEL}
AI07853c
Obsolete ^{Product(s) - Obsolete P 24.1}
SPI bus features and communication flow
The SPICLK signal is a gated clock generated from the UPSD33xx (Master) and regulates
the flow of data bits. The Master may transmit at a variety of baud rates, and the SPICLK
signal will clock one period for each bit of transmitted data. Data is shifted on one edge of
SPICLK and sampled on the opposite edge.
The SPITxD signal is generated by the Master and received by the Slave device. The
SPIRxD signal is generated by the Slave device and received by the Master. There may be
no more than one Slave device transmitting data on SPIRxD at any given time in a multi-
Slave configuration. Slave selection is accomplished when a Slave’s “Slave Select” (SS)
input is permanently grounded or asserted active-low by a Master device. Slave devices that
are not selected do not interfere with SPI activities. Slave devices ignore SPICLK and keep
their MISO output pins in high-impedance state when not selected.
The SPI specification allows a selection of clock polarity and clock phase with respect to
data. The UPSD33xx supports the choice of clock polarity, but it does not support the choice
of clock phase (phase is fixed at what is typically known as CPHA = 1). See Figure 42 and
Figure 43 on page 144 for SPI data and clock relationships.
Referring to these figures (42 and 43), when the phase mode is defined as such (fixed at
CPHA =1), in a new SPI data frame, the Master device begins driving the first data bit on
SPITxD at the very first edge of the first clock period of SPICLK.
The Slave device will use this first clock edge as a transmission start indicator, and therefore
the Slave’s Slave Select input signal may remain grounded in a single-Master/single-Slave
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Doc ID 9685 Rev 7