UPSD3354DV-40U6 Datasheet, PDF (133/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
I²C interface
Table 81. S1SETUP register bit definition
Bit
Symbol
R/W
Function
Enable Sample Setup
EN_SS = 1 will force the SIOE to sample⁽¹⁾ a START condition
7
EN_SS
R/W on the bus the number of times specified in SMPL_SET[6:0].
EN_SS = 0 means the SIOE will sample⁽¹⁾ a START condition
only one time, regardless of the contents of SMPL_SET[6:0].
6:0
SMPL_SET
[6:0]
Sample Setting
– _{Specifies the number of bus samples}⁽⁽¹⁾ _{taken during a}
START condition. See Table 82 on page 133 for values.
1. Sampling SCL and SDA lines begins after '1'-to-'0' transition on SDA occurred while SCL is high. Time
between samples is 1/f_OSC.
Table 82. Number of I²C bus samples taken after 1-to-0 transition on SDA (START
condition)
Contents of S1SETUP
t(s) ^{SS_EN bit}
c ₀
du 1
ro ₁
P ₁
te _...
ole ¹
s ₁
Ob ...
- ₁
SMPL_SET[6:0]
XXXXXXXb
0000000b
0000001b
0000010b
...
0001011b
0010111b
...
1111111b
Resulting value for
S1SETUP
00h (default)
80h
81h
82h
...
8Bh
97h
...
FFh
Resulting number of
samples taken after 1-to-0
on SDA Line
1
1
2
3
...
12
24
...
128
ct(s) _{Table 83. Start condition hold time}
rodu ^{I2C bus speed}
Range of I²C clock speed
(f_SCL)
P_Standard
Up to 100kHz
lete ^Fast
so High
101kHz to
400kHz
401kHz to 833kHz⁽¹⁾
Ob ^{1. 833kHz is maximum for UPSD33xx devices.}
Minimum START condition
hold time (t_HLDSTA)
4000ns
600ns
160ns
Note:
Table 84 provides recommended settings for S1SETUP based on various combinations of
f_OSC and f_SCL. Note that the “Total Sample Period” times in Table 83 are typically slightly
less than the minimum START condition hold time, t_HLDSTA for a given I²C bus speed.
Important: The SCL bit rate f_SCL must first be determined by bits CR[2:0] in the SFR
S1CON before a value is chosen for SMPL_SET[6:0] in the SFR S1SETUP.
Doc ID 9685 Rev 7
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