UPSD3354DV-40U6 Datasheet, PDF (257/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
DC and AC parameters
Table 177. CPLD macrocell synchronous Clock mode timing (3 V PSD module)
Symbol
Parameter
Turbo
Conditions Min Max PT Aloc
Off
Slew
rate⁽¹⁾
Unit
Maximum frequency
external feedback
1/(t_S+t_CO)
23.2
MHz
f_MAX
Maximum frequency
internal feedback
(f_CNT)
Maximum frequency
pipelined data
1/(t_S+t_CO–
10)
1/(t_CH+t_CL)
30.3
40.0
MHz
MHz
t_S Input setup time
20
+4
+ 15
ns
t_H Input hold time
0
ns
t_CH Clock high time
Clock Input 15
ns
t_CL Clock low time
Clock Input 10
) ^tCO ^{Clock to output delay Clock Input}
23
ct(s ^{tARD CPLD array delay}
Any
macrocell
20
+4
ns
–6
ns
ns
du _tMIN
Minimum clock
period⁽²⁾
t_CH+t_CL
25
ns
ro _{1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.}
te ^{P 2. CLKIN (PD1) tCLCL = tCH + tCL.}
ole Figure 91. Asynchronous RESET / Preset
s_tARPW
Ob _RESET/PRESET
- _INPUT
ct(s) REGISTER
rodu^OUTPUT
tARP
AI02864
P _{Figure 92. Asynchronous Clock mode timing (product term clock)}
te _tCHA
tCLA
ole _CLOCK
Obs ^{tSA tHA}
INPUT
REGISTERED
OUTPUT
tCOA
AI02859
Doc ID 9685 Rev 7
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