UPSD3354DV-40U6 Datasheet, PDF (205/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
27.4.33 Input Macrocells
The GPLD has 20 IMCs, one for each pin on Port A (80-pin device only), one for each pin on
Port B, and for the four pins on Port C that are not JTAG pins. The architecture of one
individual IMC is shown in Figure 67. IMCs are individually configurable, and they can strobe
a signal coming in from a port pin as a latch (gated), or as a register (clocked), or the IMC
can pass the signal without strobing, all prior to driving the signal onto the PLD input bus.
Strobing is useful for sampling and debouncing inputs (keypad inputs, etc.) before entering
the PLD AND-OR arrays. The outputs of IMCs can be read by the 8032 asynchronously
when the 8032 reads the csiop registers shown in Table 127, Table 128 on page 206, and
Table 129 on page 206. It is possible to read a PSD module port pin using one of two
different methods, one method is by reading IMCs as described here, the other method is
using MCU I/O mode described in a later section.
The optional IMC clocking or gating signal used to strobe pin inputs is driven by a product
term from the AND-OR array. There is one clocking or gating product term available for each
group of four IMCs. Port inputs 0-3 are controlled by one product term and 4-7 by another.
To specify in PSDsoft Express the method in which a signal will be strobed as it enters an
IMC for a given input pin on Port A, B, or C, just specify “PT Clocked register” to use a rising
) ^{edge to clock the incoming signal, or specify “PT Clock Latch” to use an active high gate}
t(s ^{signal to latch the incoming signal. Then define an equation for the IMC clock (.ld) or the}
IMC gate (.le) signal in the “I/O Equations” section.
uc _{If the user would like to latch an incoming signal using the gate signal ALE from the 8032,}
d _{then in PSDsoft Express, for a given input pin on Port A, B, or C, specify “Latched Address”}
ro _{as the pin function.}
P _{If it is desired to pass an incoming signal through an IMC directly to the AND-OR array}
te _{inputs without clocking or gating (this is most common), in PSDsoft Express simply specify}
le “Logic or Address” for the input pin function on Port A, B, or C.
so _{Figure 67. Detail of a single IMC}
Obsolete ^{Product(s) - Ob TO PLD INPUT BUS}
8032 READ OF PARTICULAR CSIOP IMC REGISTER
8032 DATA BIT
ALE
PIN INPUT
M
U ^{LATCHED INPUT} _{Q D}
X _{GATED INPUT}
(.LD)
PSDsoft
PSDsoft
ALE
M
U
QD
(.LE)
G
FROM I/O PORT
LOGIC
INPUT SIGNAL
FROM PIN ON
PORT A, B, or C
PT CLOCK OR GATE (.LD OR .LE) X
FROM AND-OR ARRAY
INPUT MACROCELL (IMC)
THIS SIGAL IS GANGED TO 3 OTHER
IMCs, GROUPING IMC 0 - 3 or IMC 4 - 7.
AI06603A
Doc ID 9685 Rev 7
205/272