UPSD3354DV-40U6 Datasheet, PDF (264/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

DC and AC parameters
UPSD33xx
Table 189. ISC timing (3 V PSD module)
Symbol
Parameter
Conditions Min
Max Unit
t_ISCCF Clock (TCK, PC1) frequency (except for PLD)
(1)
t_ISCCH Clock (TCK, PC1) high time (except for PLD)
(1)
t_ISCCL Clock (TCK, PC1) low time (except for PLD)
(1)
t_ISCCFP Clock (TCK, PC1) frequency (PLD only)
(2)
t_ISCCHP Clock (TCK, PC1) high time (PLD only)
(2)
t_ISCCLP Clock (TCK, PC1) low time (PLD only)
(2)
t_ISCPSU ISC Port setup time
12 MHz
40
ns
40
ns
4 MHz
90
ns
90
ns
12
ns
t_ISCPH ISC Port hold up time
t_ISCPCO ISC Port clock to output
t_ISCPZV ISC Port high-impedance to valid output
5
ns
30
ns
30
ns
t_ISCPVZ ISC Port valid output to high-impedance
) _{1. For non-PLD Programming, Erase or in ISC By-pass mode.}
t(s ^{2. For Program or Erase PLD only.}
duc Figure 97. MCU module AC measurement I/O waveform
30
ns
Pro _{VCC – 0.5V}
lete _0.45V
0.2 VCC + 0.9V
Test Points
0.2 VCC – 0.1V
so _AI06650
Ob ^{1. AC inputs during testing are driven at V}CC^{–0.5 V for a logic '1,' and 0.45 V for a logic '0.'}
- 2. Timing measurements are made at V_IH(min) for a logic '1,' and V_IL(max) for a logic '0'
t(s) ^{Figure 98. PSD module AC float I/O waveform}
uc_{VLOAD + 0.1V}
rod _{VLOAD – 0.1V}
P _{0.2 VCC – 0.1V}
Test Reference Points
VOH – 0.1V
VOL + 0.1V
te AI06651
le_{1. For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load}
o _{voltage occurs, and begins to float when a 100mV change from the loaded VOH or VOL level occurs}
Obs ^{2. IOL and IOH ≥ 20 mA}
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Doc ID 9685 Rev 7